Semiconductor Memory Internal Signal Generator Address Delay
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Solution Overview
Problem
Semiconductor memory devices, such as DDR2 SDRAM, face inefficiencies in power consumption due to unnecessary activation of flip-flops during address generation, leading to increased current consumption.
Innovation Solution
An internal signal generator is introduced that delays external addresses by predetermined latencies shorter than those set by the semiconductor memory device, selecting appropriate delay addresses to generate internal read and write addresses, thereby reducing power consumption by deactivating unused flip-flops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all flip-flops are activated for address generation, then address generation functionality is ensured, but current consumption increases
Solution Approach 1:
The address generation unit is divided into multiple segments corresponding to different latency settings (e.g., first address generation unit for AL=3, second for AL=2, third for AL=1). Each segment contains only the flip-flops necessary for its specific latency requirement. This segmentation allows the system to activate only the relevant segment based on the configured latency, thereby reducing current consumption while maintaining address generation functionality.
2Use of energy by moving object
If flip-flops are deactivated to reduce power consumption, then current consumption decreases, but address generation capability is compromised
Solution Approach 1:
The system dynamically selects which address generation unit to activate based on the configured additive latency value. Control logic determines the appropriate latency setting and enables only the corresponding address generation unit (first unit for AL=3, second for AL=2, third for AL=1). This dynamic activation ensures that the minimum necessary flip-flops are always active, maintaining address generation capability while minimizing power consumption.
Data Source
AI summary
An internal signal generator for use in a semiconductor memory device includes an internal read address generation unit and an internal write address generation unit. The internal read address generation unit generates a plurality of read delay addresses by delaying an external address for a predetermined latency shorter than an additive latency set by the semiconductor memory device and selects one of the read delay addresses to thereby output an internal read address. The internal write address generation unit generates a plurality of write delay addresses by delaying the internal read address for a preset latency shorter than a column address strobe (CAS) latency set by the semiconductor memory device and selects one of the write delay addresses to thereby output an internal write address.