Memory Signal Line Split Termination Without Separate VTT
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Solution Overview
Problem
Memory systems that use daisy-chain or fly-by topologies for command/address signal lines require separate termination voltages, increasing cost due to additional voltage regulators, as multiple memory devices modify the effective impedance of signal lines.
Innovation Solution
Implementing a split-termination configuration using external impedance coupled to VDD and adjustable internal impedance, such as on-die termination, which allows for balanced or unbalanced termination without a separate termination voltage, reducing power consumption and eliminating the need for termination control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate termination voltage is applied to termination impedance in daisy-chain topology, then signal communication reliability is improved, but device complexity and cost increase due to additional voltage regulators
Solution Approach 1:
The patent merges the termination function with existing power supply infrastructure by applying termination voltage through the VDD power rail that is already present for memory device operation. This eliminates the need for separate termination voltage regulators while maintaining signal integrity through proper impedance matching at the signal line terminations.
Solution Approach 2:
The VDD power supply line is made multi-functional by serving both as the operational power supply for memory devices and as the termination voltage source for signal lines. This universal usage of the power rail eliminates dedicated termination voltage infrastructure while maintaining both power delivery and signal termination functions.
2Reliability
If separate termination voltage is applied to termination impedance, then signal communication reliability is improved, but manufacturing cost increases due to additional voltage regulators
Solution Approach 1:
The patent combines the termination voltage function with the existing VDD power supply, eliminating the need for separate termination voltage regulators. This merging of functions reduces the bill of materials and manufacturing complexity while maintaining signal communication reliability through proper impedance termination.
3Quantity of substance
If multiple memory devices are coupled in parallel to signal lines, then system integration density is improved, but signal line impedance control becomes difficult due to impedance modification by parallel devices
Solution Approach 1:
The patent applies termination impedance at specific locations along the signal line (at memory device interfaces) to locally compensate for impedance variations caused by parallel-coupled devices. This localized impedance control maintains signal integrity despite the presence of multiple parallel memory devices on the same signal line.
Data Source
AI summary
Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance outside of the memory controller and an internal impedance within the memory controller. The memory controller does not activate the external impedance prior to communicating the signals and, therefore, does not deactivate the external impedance after communicating the signals. The internal impedance of the memory controller can be enabled or disabled in order to reduce interface power consumption. Moreover, the internal impedance may be implemented using a passive component, an active component or both. For example, the internal impedance may include either or both an on-die termination and at least one driver.