Vertical-Channel Memory Silicide Layout for Alignment Distortion
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Solution Overview
Problem
The wafer bonding process in dynamic random-access memory (DRAM) devices leads to difficulties in photolithography alignment due to shrinking device sizes, resulting in reduced yield and performance uniformity, as well as local distortion causing misalignment of drains and bit lines, which increases contact resistance and circuit breakages.
Innovation Solution
A method involving the formation of first and second spacers in a semiconductor material layer, with silicidation of semiconductor material strips between the spacers to create silicide layers that are self-aligned, ensuring proper alignment and electrical connection even with distorted transistor pillars.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If wafer bonding process is used to form vertical-channel memory device, then chip area is reduced, but photolithography alignment becomes difficult and yield decreases
Solution Approach 1:
The patent performs alignment mark formation and photolithography patterning on the front surface of the semiconductor wafer before wafer bonding occurs. This preliminary action allows alignment to be established when the wafer is still accessible from the front, avoiding the alignment difficulties that arise after bonding when only backside access remains.
Solution Approach 2:
Instead of performing photolithography alignment after wafer bonding (backside process), the patent inverts the sequence by completing the alignment-critical photolithography steps before bonding. This reversal transforms a difficult backside alignment problem into a manageable frontside process.
2Device complexity
If wafer bonding process is used, then vertical-channel structure is achieved, but local distortion occurs causing drain misalignment and circuit breakages
Solution Approach 1:
The patent forms the drain structures and performs critical alignment operations on the front surface before wafer bonding. This preliminary formation of drains ensures they are positioned correctly before any bonding-induced distortion occurs, preventing misalignment and circuit breakages that would result from post-bonding distortion.
Solution Approach 2:
The patent anticipates bonding-induced distortion by completing all alignment-critical structures (drains, alignment marks) before bonding. This beforehand cushioning protects against future misalignment by establishing the correct geometry prior to the distorting bonding process.
3Area of stationary object
If backside process is used for drain formation, then chip area is reduced, but alignment difficulty increases and contact resistance increases
Solution Approach 1:
The patent inverts the conventional backside-process approach by performing drain formation and alignment-critical operations on the front surface before bonding. This inversion maintains the area benefits of vertical-channel structure while eliminating the alignment difficulties inherent in backside processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the alignment and electrical connectivity of memory device components, reducing the risk of circuit failures and resistance-capacitor delays, thereby improving the yield and uniformity of DRAM device performance.
Implementation Method 1
performing a silicidation process at the second surface of the semiconductor material layer to convert at least portion of each of the semiconductor material strips into a silicide layer
Data Source
AI summary
A method of forming a memory device including providing a base wafer including a semiconductor material layer, and forming first and second spacers in the semiconductor material layer. The first spacers extend from a first surface of the semiconductor material layer to a second surface of the semiconductor material layer. The second spacers cross the first spacers and extend from the first surface of the semiconductor material layer to a position inside the semiconductor material layer. A plurality of semiconductor material strips are formed each between bottoms of the second spacers and the second surface of the semiconductor material layer and sandwiched between two neighboring first spacers. The method further includes performing a silicidation process at the second surface of the semiconductor material layer to convert at least portion of each of the semiconductor material strips into a silicide layer.