3D Memory Slit Cavity Structure for Select Gate Isolation
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Solution Overview
Problem
The miniaturization of semiconductor storage devices with three-dimensional memory cell arrays is hindered by poor etching controllability of metal conductive layers, leading to tapered slits that require deep and wide openings, increasing the number of dummy word lines and contradicting the miniaturization goal.
Innovation Solution
The implementation of a semiconductor storage device with a stacked body featuring alternately layered conductive and insulating materials, where a slit is formed with a narrow width at the bottom portion by overlaying an insulating film on the upper opening, creating a cavity within the slit to ensure electrical isolation of select gates without excessive depth or width, thereby reducing the layout area and number of dummy word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the slit depth and bottom width are increased to ensure electrical isolation of select gates, then the electrical isolation is improved, but the memory cell array size increases and miniaturization is hindered
Solution Approach 1:
The patent introduces a dummy word line layer in the vertical stacking direction to achieve electrical isolation, rather than increasing the horizontal slit dimensions. This moves the isolation function from the planar dimension to the vertical dimension, allowing narrow slits while maintaining isolation through the additional conductive layer that extends across the slit at a different height level
Solution Approach 2:
The dummy word line acts as an intermediary conductive element that bridges the electrical isolation requirement. It is positioned within the slit structure and connected to select gates, providing the necessary electrical separation between adjacent select gates without requiring the slit to be wide or deep
2Reliability
If metal material is used for the conductive layer, then the electrical conductivity is improved, but the etching controllability deteriorates causing tapered slit profile
Solution Approach 1:
The conductive structure is segmented into functional portions: the select gate conductive layer uses metal material for high conductivity where needed, while the dummy word line portion within the slit is formed using a different material or structure that is more amenable to etching control. This segmentation allows each portion to be optimized for its specific function
Solution Approach 2:
Different regions of the conductive structure have different properties: the select gate regions require high conductivity (metal), while the isolation region (dummy word line) requires good etching controllability. The patent applies different materials or formation methods to different local regions to satisfy both requirements
3Reliability
If the number of dummy word lines is increased to achieve electrical isolation, then the isolation effectiveness is improved, but the device complexity and manufacturing steps increase
Solution Approach 1:
The dummy word line serves multiple functions simultaneously: it provides electrical isolation between select gates, maintains the stacked body structure continuity, and enables planarization for subsequent processing steps. This multi-functionality reduces the need for additional dedicated isolation structures
Data Source
AI summary
According to one embodiment, a semiconductor storage device includes a substrate; a stacked body provided above the substrate, wherein the stacked body includes a plurality of first insulating layers and a plurality of conductive layers that are alternately stacked on top of one another along a vertical direction; a plurality of columnar portions that penetrate the stacked body; a first slit, provided in the vertical direction, that divides one or more of the plurality of conductive layers at least at an upper portion of the stacked body; and a second insulating layer that overlays an opening of the first slit, which forms a cavity.