Non-Volatile Memory Soft-Bit Sensing With Shifted Read Point
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Solution Overview
Problem
Current memory systems require additional reads to generate soft bit data for error correction, leading to increased power consumption and performance losses, as they often rely on multiple read values to determine the reliability of hard bit data, especially for memory cells with threshold voltages near the read level.
Innovation Solution
An efficient soft sense read mode is introduced, which reduces the number of read values needed by shifting the hard bit read point and combining hard and soft bit sensing into a single operation, using a single soft bit read to provide reliability information only for less reliable hard bit values, and optimizing sense amplifier operations to minimize overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple read values are performed to generate soft bit data for error correction, then the reliability of hard bit data is improved, but power consumption increases
Solution Approach 1:
The patent extracts and processes only the necessary soft bit information selectively. Instead of performing multiple reads for all data, the system identifies and processes only those memory cells that require soft bit generation (those with threshold voltages near the read level), thereby reducing overall power consumption while maintaining reliability where needed.
Solution Approach 2:
The patent applies partial action by performing soft bit sensing only on a subset of memory cells rather than all cells. The system determines which cells need soft bit processing based on their threshold voltage proximity to the read level, applying the additional read operation only where necessary to improve reliability without unnecessarily consuming power across the entire memory array.
2Reliability
If multiple read values are performed to generate soft bit data, then error correction capability is improved, but performance deteriorates
Solution Approach 1:
The patent extracts soft bit information only from memory cells that require it, rather than processing all cells uniformly. This selective extraction approach maintains error correction capability for problematic cells while avoiding the performance penalty of processing entire memory arrays, thus preserving overall read performance.
Solution Approach 2:
The system applies soft bit sensing partially only to memory cells with threshold voltages near the read level. This partial application of the multi-read process maintains error correction capability where needed while significantly reducing the performance impact compared to applying the process to all memory cells.
3Use of energy by moving object
If a single soft bit read is performed to provide reliability information, then power consumption is reduced, but the amount of soft bit data generated is limited
Solution Approach 1:
The patent applies local quality by providing reliability information selectively to specific memory cells rather than generating uniform soft bit data across all cells. The single soft bit read operation targets only those cells with threshold voltages near the read level, consuming less power while generating the appropriate amount of soft bit data where actually needed for error correction.
4Speed
If hard and soft bit sensing are combined into a single operation, then read speed is improved, but sensing complexity increases
Solution Approach 1:
The patent merges hard bit sensing and soft bit sensing into a single unified operation. By combining these sensing modes, the system improves read speed as the patent states, though this integration necessarily increases sensing complexity. The merged operation allows simultaneous extraction of both hard bit and soft bit information in one sensing pass.
Data Source
AI summary
A non-volatile memory combines a hard bit and a soft bit read into a single, efficient soft sense sequence by using two sense per state level to improve read time efficiency. Rather than a standard hard bit read, where two soft bit reads are performed, offset above and below the hard bit read value, the hard bit read is shifted so that it reliable senses one state but less reliably senses the other state and soft bit data is only determined for the less reliably sensed state. This reduces the amount of soft bit data. The efficient soft sense sequence can be used as a default read mode, providing soft bit information for ECC correction without triggering a read error handling flow. Merging the soft bit and hard bit sense into one sequence can avoid extra overhead for read sequence operations.