3D Memory Source Pattern Layout for Smaller Cell-Peripheral Footprint
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in integrating memory cell arrays and peripheral circuits efficiently, leading to increased two-dimensional area occupation.
Innovation Solution
A semiconductor memory device design featuring a net-shaped first source pattern with openings, a second source pattern, and a cell-array-side pad pattern bonded directly to the first source pattern, along with a bit line structure that overlaps with the peripheral-circuit-side pad pattern, facilitating electrical connection between the peripheral circuit and memory cell array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory cell array and peripheral circuit are integrated in conventional layout, then functional integration is achieved, but two-dimensional area occupation increases
Solution Approach 1:
The patent transitions from a two-dimensional planar layout to a three-dimensional stacked architecture where the memory cell array is positioned vertically above the peripheral circuit. This vertical stacking enables both components to coexist in the same footprint area, reducing the overall two-dimensional area occupation while maintaining full functional integration between the memory cell array and peripheral circuit.
Solution Approach 2:
The patent implements a nested configuration where the memory cell array is effectively placed within the vertical space above the peripheral circuit structure. The source pattern acts as a shared interface layer that connects both the peripheral circuit below and the memory cell array above, creating a compact nested arrangement that maximizes space utilization.
2Area of stationary object
If source pattern is made net-shaped with openings, then area is reduced and integration is enhanced, but manufacturing complexity increases
Solution Approach 1:
The source pattern is segmented into a net-shaped configuration with multiple openings rather than a solid continuous structure. This segmentation reduces the material usage and occupied area of the source pattern while maintaining its electrical connectivity function. The openings allow underlying structures to be accessed or reduce capacitance, and the segmented design can be fabricated using standard photolithography patterning processes.
3Device complexity
If cell-array-side pad pattern is bonded directly to first source pattern, then electrical connection is simplified, but manufacturing precision requirements increase
Solution Approach 1:
The cell-array-side pad pattern and the first source pattern are merged into a bonded configuration where they are directly connected to each other. This merging eliminates the need for separate intermediate connection structures, simplifying the overall electrical connection architecture. The direct bonding reduces the number of fabrication steps and potential failure points, although it does require precise alignment during the bonding process to ensure proper electrical connectivity.
Data Source
AI summary
There are provided a semiconductor memory device and a manufacturing method of the same. The semiconductor memory device includes: a peripheral circuit structure with a page buffer group; a net-shaped first source pattern disposed on the peripheral circuit structure, the net-shaped first source pattern with a plurality of openings; a memory cell array disposed on the net-shaped first source pattern; a second source pattern disposed between the net-shaped first source pattern and the memory cell array; and a cell-array-side pad pattern, disposed between the net-shaped first source pattern and the second source pattern, extending toward the net-shaped first source pattern from the second source pattern, the cell-array-side pad pattern being bonded directly to the net-shaped first source pattern.