Semiconductor Memory Device Source Line Potential Equalization
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Solution Overview
Problem
NAND flash memory devices face issues with erroneous data reading due to variations in the potential of the source line, which affect the potential difference between the source line and the bit line, leading to reduced operational reliability and increased threshold voltage distribution.
Innovation Solution
The semiconductor memory device includes a well driver that electrically connects the source line to the p-type well region, allowing the potential of the well region to be equalized with the source line during read operations, and a bit line driver that varies the potential of the bit line in conjunction with the source line, minimizing the impact of source line variations on the word line and back gate potential.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If NAND flash memory reads data from multiple memory cells simultaneously, then reading efficiency is improved, but source line potential variation increases causing erroneous data reading
Solution Approach 1:
The patent applies equipotentiality by connecting the back gate to the source line, ensuring they maintain the same potential during read operations. This eliminates potential differences between source line and back gate that would otherwise cause erroneous data reading when multiple cells are read simultaneously, while still allowing high reading efficiency through parallel operation of multiple memory cells.
2Adaptability or versatility
If source line potential varies during read operations, then more memory cells can be accessed, but threshold voltage distribution widens reducing operational reliability
Solution Approach 1:
By maintaining the back gate at the same potential as the source line through direct connection, the patent eliminates the harmful potential differences that would otherwise widen threshold voltage distribution. This allows versatile access to multiple memory cells while maintaining narrow threshold voltage distribution and high operational reliability.
3Measurement precision
If word line potential is increased to compensate for source line variation, then data reading accuracy improves, but programming voltage requirements increase
Solution Approach 1:
The patent achieves data reading accuracy not by increasing word line potential, but by making the back gate equipotential with the source line. This eliminates the need for compensatory word line voltage increases, thereby maintaining accurate data reading while avoiding increased programming voltage requirements and energy consumption.
Data Source
AI summary
A semiconductor memory device includes memory cells, a source line, a word line, a bit line, and a driver circuit. The memory cells are formed on a semiconductor layer and have a charge accumulation layer and a control gate on the charge accumulation layer. The word line is connected to gate of the memory cell. The bit line is electrically connected to a drain of the memory cell. The source line is electrically connected to a source of the memory cell. The driver circuit varies potential of the semiconductor layer in conjunction with potential of the source line.