Memory Clock Synchronization Switching for Stable Host Link Setup
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Solution Overview
Problem
Existing memory systems face instability in communication connections with hosts due to unfixed potential in initialization processing, leading to unstable link states when different clock signals are used by the host and memory system.
Innovation Solution
A memory system with a control circuit that transitions between CC and SRIS modes based on specific interrupts, allowing for dynamic switching of clock modes through a state transition table and multiplexer control, ensuring stable communication by aligning host and memory system clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the memory system uses different clock signals than the host during initialization, then the memory system can operate independently, but the communication connection becomes unstable due to unfixed potential
Solution Approach 1:
The patent implements dynamic clock mode switching between CC (Common Clock) and SRIS (Separate Reference Independent Spread) modes based on operational state. The control circuit transitions between these modes according to initialization completion status and operational requirements, allowing the system to adapt its clock synchronization behavior dynamically rather than being fixed in one mode
Solution Approach 2:
The patent changes the clock synchronization parameter from independent (SRIS) to synchronized (CC) based on operational state. During initialization, the system operates in SRIS mode with separate clock signals for independent operation. After initialization completion, it transitions to CC mode where both host and memory system use the same reference clock signal, eliminating unfixed potential issues
2Adaptability or versatility
If the memory system switches communication modes dynamically, then it can adapt to different clock signals, but the control complexity increases
Solution Approach 1:
The control circuit automatically determines when to switch between CC and SRIS modes based on initialization completion detection and operational state, without requiring external control or complex management logic. The system self-manages the mode transition based on internal state monitoring
Solution Approach 2:
The control circuit is designed to handle multiple functions: initialization processing, operational state monitoring, mode determination, and clock signal coordination. This multi-functional design consolidates control logic into a single circuit that can manage both CC and SRIS modes
Data Source
AI summary
A memory system includes a memory, a control circuit, and an interface circuit. The interface circuit includes a first terminal capable of receiving a first clock supplied from an outside, and a second terminal capable of receiving a first signal. When in a first state, the control circuit transitions to a second state in response to input of a first signal, and to a third state in response to input of the first clock. When in the second state, the control circuit executes initialization processing of a first mode for an operation based on an internally generated second clock or is in an operable state in the first mode, and ends the operable state in the first mode in response to input of the first clock and transitions to the third state. When in the third state, the control circuit transitions to a fourth state in response to input of the first signal. When in the fourth state, the control circuit executes initialization processing of a second mode for an operation based on the first clock or is in an operable state in the second mode.