3D Memory Stack Common Source Line Vertical Interconnection
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Solution Overview
Problem
The increasing complexity of memory devices in integrated circuits (ICs) has led to a need for improved integration density and electrical characteristics, with existing technologies struggling to efficiently manage the downscaled memory cells and intricate operating circuits.
Innovation Solution
The proposed IC device incorporates a peripheral circuit structure with a memory stack featuring overlapping gate lines, a through hole in the upper substrate, and a common source line that extends through this hole to connect with the peripheral circuit, enhancing integration density and layout design freedom while improving interconnection reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells are downscaled to increase integration density, then integration density is improved, but manufacturing precision and reliability deteriorate
Solution Approach 1:
The patent transitions from planar 2D memory cell arrangement to 3D vertical stacking architecture. Memory stacks are formed vertically on the substrate, with multiple gate lines (first gate line, second gate line, third gate line) stacked in the vertical direction. This dimensional change allows significant increase in integration density without further downsizing individual memory cells, thereby avoiding the manufacturing precision and reliability issues associated with continued scaling.
Solution Approach 2:
The memory device is segmented into multiple functional layers and regions. The memory stack is divided into distinct gate line layers (first, second, third gate lines) separated by insulating structures. Word line cut regions are introduced to segment the word lines, allowing independent control and routing. This segmentation enables complex 3D interconnection while maintaining manufacturability and reliability of each individual component.
2Adaptability or versatility
If operating circuits and interconnection structures are made more complicated to enable memory device operations, then functionality is improved, but device complexity increases
Solution Approach 1:
The patent utilizes vertical stacking to implement multiple gate lines (first gate line, second gate line, third gate line) in the vertical direction, enabling complex memory operations without requiring complex planar interconnection. The 3D arrangement allows selective activation of different gate lines for read, write, and erase operations, providing full functionality while maintaining relatively simple interconnection structures through vertical alignment rather than complex lateral routing.
Solution Approach 2:
The memory stack structure with multiple gate lines serves multiple functions: the first gate line for word line selection, the second gate line for string selection, and the third gate line for ground selection. This multi-functional design enables complete memory operations (read, write, erase) using a unified vertical stack architecture, reducing the need for separate dedicated circuits for each function and thereby managing device complexity.
3Productivity
If chip size is reduced to improve integration, then integration density is improved, but interconnection reliability deteriorates
Solution Approach 1:
The patent employs vertical interconnection through through-electrodes that penetrate multiple gate line layers and insulating structures in the vertical direction. This 3D interconnection approach allows efficient routing of bit lines and word lines through the stacked memory structure without requiring large lateral chip area. The vertical alignment of through-electrodes with contact holes ensures reliable electrical connection while maintaining compact chip footprint.
Solution Approach 2:
The patent implements nested interconnection structures where through-electrodes are positioned within word line cut regions, and contact holes are formed through insulating structures to connect different vertical layers. The through-electrodes are nested within the vertical stack, connecting the memory cell region to peripheral circuits below. This nested arrangement maximizes interconnection density and reliability within the constrained vertical space of the chip.
Data Source
AI summary
An integrated circuit (IC) device includes a peripheral circuit structure, a memory stack including a plurality of gate lines overlapping the peripheral circuit structure in a vertical direction on the peripheral circuit structure, an upper substrate between the peripheral circuit structure and the memory stack, the upper substrate including a through hole positioned below a memory cell region of the memory stack, a word line cut region extending lengthwise in a first lateral direction across the memory stack and the through hole, and a common source line located in the word line cut region, the common source line including a first portion extending lengthwise in the first lateral direction on the upper substrate and a second portion integrally connected to the first portion, the second portion penetrating the upper substrate through the through hole from an upper portion of the upper substrate and extending into the peripheral circuit structure.