3D Memory Stack Contact Plug Penetration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current two-dimensional (2D) semiconductor memory devices face limitations in integration density due to high-cost fine pattern forming technologies, necessitating the development of three-dimensional (3D) memory devices with reduced manufacturing costs and reliable product characteristics.
Innovation Solution
A semiconductor device with a stack structure featuring alternately stacked first and second insulating layers, where contact plugs penetrate these layers to connect horizontal electrodes, eliminating the need for additional insulating layers and enhancing integration density without increasing manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional insulating layers are formed between contact plugs and horizontal electrodes, then electrical insulation is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent removes the additional insulating layer from the structure, relying instead on the vertical positioning of the contact plug within the tunnel insulating layer to provide electrical insulation. This extraction of the unnecessary component simplifies the device structure while maintaining insulation functionality through the inherent layer arrangement.
Solution Approach 2:
The tunnel insulating layer serves multiple functions: it provides electrical insulation between the contact plug and horizontal electrode, and simultaneously serves as part of the memory cell structure. By making the insulating layer multi-functional, the patent eliminates the need for separate additional insulating layers, reducing structural complexity.
2Reliability
If additional insulating layers are formed between contact plugs and horizontal electrodes, then electrical insulation is improved, but manufacturing cost and process steps increase
Solution Approach 1:
The patent eliminates the additional insulating layer formation step from the manufacturing process, reducing both material costs and process complexity. The insulation function is achieved through the existing tunnel insulating layer and contact plug positioning, requiring no extra fabrication steps.
Solution Approach 2:
The tunnel insulating layer is formed beforehand as part of the memory cell structure, and the contact plug is subsequently positioned within it. This preliminary formation of the insulating layer with inherent insulation capabilities eliminates the need for later additional insulating layer formation, simplifying the manufacturing process.
3Ease of manufacture
If 2D memory device layout is used, then manufacturing process is simpler, but integration density is limited
Solution Approach 1:
The patent transitions from a two-dimensional layout to a three-dimensional structure by forming the contact plug vertically within the tunnel insulating layer. This vertical arrangement allows memory cells to be stacked in the vertical dimension, significantly increasing integration density while maintaining manufacturing simplicity through standard semiconductor fabrication processes.
Data Source
AI summary
A semiconductor device includes a plurality of first insulating layers and a plurality of second layers alternately and vertically stacked on a substrate. Each of the plurality of second layers includes a horizontal electrode horizontally separated by a second insulating layer. A contact plug penetrates the plurality of first insulating layers and the second insulating layer of the plurality of second layers.