Multi-Die Memory Stack Dicing to Reduce Bonding Voids
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Solution Overview
Problem
The existing dicing procedures for forming multi-die memory stacks result in silicon particles and residues on the memory die surfaces, leading to bonding voids and reduced yield due to increased deposits when multiple memory dies are diced together, which affects the integrity and functionality of the semiconductor components.
Innovation Solution
A dicing procedure is performed to etch cavities through dielectric and silicon materials in a scribe structure between memory stacks, using incremental etching techniques to mitigate silicon particle deposition and reduce bonding voids, thereby increasing yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple memory dies are diced together from respective wafers to form multi-die memory stacks, then productivity is improved by forming complete stacks in fewer dicing steps, but manufacturing precision deteriorates due to silicon particles and residues accumulating on memory die surfaces, leading to bonding voids and reduced yield
Solution Approach 1:
The dicing process is segmented into separate operations: first dicing memory dies from first wafers, then dicing memory dies from second wafers. This segmentation prevents cumulative particle deposition that would occur if multiple dies were diced together in a single operation, thereby maintaining bonding quality while still improving productivity by forming complete stacks in fewer overall steps.
Solution Approach 2:
Memory dies are diced from their respective wafers before being bonded together to form the multi-die stack. This preliminary dicing action ensures that each die is separated and cleaned individually, preventing the accumulation of silicon particles and residues on bonding surfaces that would occur if multiple dies were diced together, thus maintaining high bonding quality.
2Manufacturing precision
If incremental etching techniques are used to mitigate silicon particle deposition, then manufacturing precision is improved by reducing bonding voids, but device complexity increases due to additional process steps
Solution Approach 1:
The dicing process is divided into sequential steps where memory dies are diced from different wafers in separate operations. This segmentation inherently reduces silicon particle deposition on bonding surfaces without requiring complex incremental etching techniques, thus improving bonding quality while maintaining relatively simple process equipment and procedures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The described dicing method reduces silicon particle and residue accumulation, enhancing the bonding quality and yield of multi-die memory stacks by minimizing voids and improving manufacturing efficiency.
Implementation Method 1
A dicing procedure is performed to etch cavities through dielectric and silicon materials in a scribe structure between memory stacks
Data Source
AI summary
Methods, systems, and devices for dicing multi-die memory stacks are described. For example, a manufacturing system may form a stack including a silicon material, a first memory stack, a second memory stack, and a scribe structure between the first memory stack and the second memory stack. The first memory stack includes a first memory die coupled with a second memory die and the second memory stack includes a third memory die coupled with a fourth memory die. As such, the manufacturing system may perform a dicing procedure to dice, or separate, the first memory stack and the second memory stack from the scribe structure. Accordingly, the manufacturing system may bond the first memory die of the first memory stack with a first logic die and the third memory die of the second memory stack with a second logic die based on the dicing procedure.