3D Memory Stack Dielectric Trench Layout for Leakage Control
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Solution Overview
Problem
Conventional methods for forming microelectronic devices, such as 3D NAND Flash memory devices, face challenges with increased feature packing densities leading to undesirable stresses, defects, and current leaks, which diminish memory device performance, reliability, and durability.
Innovation Solution
The method involves forming a microelectronic device structure with a stack structure comprising alternating insulative and conductive tiers, a dielectric structure extending through the stack, and additional dielectric materials to alleviate stresses and prevent current leaks by creating trenches and filling them with dielectric material, which also facilitates the formation of contact structures and conductive pillars.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature packing density is increased to enhance memory density, then memory density is improved, but undesirable stresses, defects, and current leaks increase
Solution Approach 1:
The patent divides the memory device structure into multiple decks (upper deck and lower deck) with separate formation processes. Each deck is formed independently with its own contact structures, allowing stress and defects to be isolated within individual decks rather than propagating across the entire structure. This segmentation maintains high memory density while improving reliability by containing potential failures within localized regions.
Solution Approach 2:
The patent performs preliminary stress relief actions during the formation process by creating trenches and filling them with dielectric material before forming contact structures. This preliminary action prevents stress accumulation that would otherwise lead to defects and current leaks during subsequent processing, thereby maintaining device reliability at high packing densities.
2Quantity of substance
If conventional formation methods are used to achieve high memory density, then memory density is improved, but manufacturing precision deteriorates due to access line contact over etch stresses and punch through defects
Solution Approach 1:
The patent segments the contact structure formation into separate processes for upper deck and lower deck. Each deck's contact structures are formed independently with controlled etching parameters, preventing over-etch stresses from affecting the entire structure. This segmentation maintains manufacturing precision while achieving high memory density through multi-deck architecture.
Solution Approach 2:
The patent performs preliminary trench formation and dielectric filling before contact structure formation. This preliminary action creates a stable foundation that prevents access line contact punch through defects during subsequent etching processes, thereby maintaining manufacturing precision at high packing densities.
3Quantity of substance
If conventional dual deck configuration is used to enhance memory density, then memory density is improved, but current leaks increase due to select gate current leakage and access line current leakage
Solution Approach 1:
The patent segments the electrical isolation into separate dielectric structures for upper and lower decks. Each deck has its own isolation dielectric that prevents current leakage within that deck, and the decks are further isolated from each other. This segmented isolation approach maintains high memory density while minimizing current leakage by containing potential leakage paths within individual decks.
Solution Approach 2:
The patent performs preliminary dielectric structure formation and trench filling before contact structure formation. This preliminary action creates complete electrical isolation paths that prevent select gate current leakage and access line current leakage during subsequent processing and operation, thereby eliminating current leakage issues while maintaining high memory density.
Data Source
AI summary
A method of forming a microelectronic device comprises forming a microelectronic device structure. The microelectronic device structure comprises a stack structure comprising insulative structures and additional insulative structures vertically alternating with the insulative structures, a dielectric structure vertically extending partially through the stack structure, and a dielectric material vertically overlying and horizontally extending across the stack structure and the dielectric structure. Portions of at least the dielectric material and the dielectric structure are removed to form a trench vertically overlying and at least partially horizontally overlapping a remaining portion of the dielectric structure. The trench is substantially filled with additional dielectric material. Microelectronic devices, memory devices, and electronic systems are also described.