3D Memory Stack Coupling With Etch-Resistant Isolation Tier
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Solution Overview
Problem
Current memory circuitry technologies face challenges in efficiently forming memory arrays with vertically-stacked memory cells, particularly in ensuring direct electrical coupling and reducing the risk of etching through integrated circuitry components, while maintaining structural integrity and electrical isolation between memory blocks.
Innovation Solution
The method involves forming a lower stack with vertically-alternating insulative and conductive tiers, followed by an upper stack with select-gate transistors, where individual upper channel-material strings are directly electrically coupled to lower channel-material strings, and an insulator tier of different composition is used to reduce etching risks and provide lateral electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If vertically-stacked memory cells are formed with direct electrical coupling between upper and lower channel-material strings, then electrical coupling efficiency is improved, but the risk of etching through integrated circuitry components increases
Solution Approach 1:
The patent introduces an intermediary insulator tier between the upper and lower memory stacks. This insulator tier acts as a mediator that prevents direct etching through the integrated circuitry components while still allowing electrical coupling through conductive vias. The insulator tier composition is specifically selected to be resistant to etching processes, thereby protecting the underlying structures without compromising the electrical connection.
Solution Approach 2:
The insulator tier is formed in advance before the etching process that creates the vertical connections. This preliminary action of depositing the etch-resistant insulator material protects the integrated circuitry components from being etched through during subsequent processing steps, while still allowing the formation of conductive pathways for electrical coupling.
2Reliability
If an insulator tier of different composition is inserted between upper and lower stacks, then etching risk is reduced and lateral electrical isolation is improved, but device complexity increases
Solution Approach 1:
The insulator tier serves multiple functions simultaneously: it provides etch resistance to prevent damage during processing, provides lateral electrical isolation between adjacent memory blocks, and serves as a structural foundation for the upper stack. By combining multiple functions into a single tier, the patent reduces the need for additional separate components, thereby limiting the increase in device complexity.
Solution Approach 2:
The patent merges the etch protection function and the electrical isolation function into a single insulator tier structure. Rather than using separate layers for etch protection and isolation, the insulator tier combines both functions, simplifying the overall structure compared to using multiple independent components.
3Productivity
If vertically-stacked memory cells are formed with direct electrical coupling, then manufacturing efficiency is improved, but structural integrity between memory blocks is compromised
Solution Approach 1:
The patent segments the memory structure into distinct upper and lower stacks separated by the insulator tier. This segmentation allows each stack to be formed and processed independently, maintaining structural integrity and preventing interference between memory blocks, while still enabling electrical coupling through the conductive vias that penetrate the insulator tier.
Data Source
AI summary
A method used in forming a memory array comprising strings of memory cells comprises forming a lower stack comprising vertically-alternating different-composition lower first tiers and lower second tiers. The lower stack comprises lower channel-material strings extending through the lower first tiers and the lower second tiers. An upper stack is formed directly above the lower stack. The upper stack comprises vertically-alternating different-composition upper first tiers and upper second tiers. The upper stack comprises upper channel-material strings of select-gate transistors. Individual of the upper channel-material strings are directly electrically coupled to individual of the lower channel-material strings. The upper and lower first tiers are conductive at least in a finished-circuitry construction. The upper and lower second tiers are insulative and comprise insulative material. An insulator tier comprising insulator material is directly below a lowest of the upper first tiers and directly above an uppermost of the lower first tiers. The insulator material is of different composition from that of the insulative material of the upper second tiers and of different composition from that of the insulative material of the lower second tiers. Other embodiments, including structure, are disclosed.