3D Memory Stack Doped Pocket for Threshold Voltage Uniformity
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Solution Overview
Problem
Current three-dimensional semiconductor devices, such as vertical NAND strings, face challenges in achieving uniform threshold voltages across multiple memory stack structures due to variations in dopant profiles, leading to inconsistencies in device performance.
Innovation Solution
A monolithic three-dimensional memory device structure is developed, featuring a stack of alternating insulating and conductive layers with a doped pocket region surrounding the source region, where the doped pocket region has a higher dopant concentration of the first conductivity type, and an interface between the doped pocket region and the semiconductor region underlies at least one memory stack structure, allowing for controlled dopant diffusion during an anneal process to achieve uniform threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional doping methods are used in three-dimensional vertical NAND strings, then manufacturing process is simple, but threshold voltage uniformity across memory stack structures deteriorates
Solution Approach 1:
The substrate is divided into multiple regions with different doping characteristics: a first region with first-type dopant and a second region with second-type dopant. This segmentation allows independent control of doping profiles in different areas, enabling precise threshold voltage uniformity across outer and inner memory stack structures while maintaining a manageable manufacturing process
Solution Approach 2:
Different dopant concentrations and types are applied to different spatial regions: the first region receives first-type dopant at a first concentration, while the second region receives second-type dopant at a second concentration. This local quality approach ensures that each region's doping is optimized for its specific position, achieving uniform threshold voltages without requiring complex global doping structures
2Manufacturing precision
If dopant concentration is increased to compensate for threshold voltage variations, then threshold voltage uniformity improves, but dopant diffusion control becomes more difficult
Solution Approach 1:
The patent uses counterbalancing doping strategies where first-type and second-type dopants are applied in complementary regions with carefully controlled concentrations. The first region's doping profile compensates for variations affecting outer stacks, while the second region's doping profile compensates for variations affecting inner stacks, achieving uniformity without excessive dopant concentrations that would cause uncontrolled diffusion
Solution Approach 2:
Doping regions are pre-configured with specific dopant types and concentrations before memory stack formation. The first region is doped with first-type dopant and the second region with second-type dopant in advance, establishing controlled doping profiles that prevent subsequent threshold voltage variations without requiring high dopant concentrations that would lead to diffusion issues
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution ensures that the threshold voltages of field effect transistors in both outer and inner memory stack structures are within a predefined tolerance, minimizing the differential and enhancing the uniformity and performance of the memory device.
Implementation Method 1
The first and second conductivity type dopants are simultaneously outdiffused employing an anneal process performed at an elevated temperature
Implementation Method 2
employing an anneal process performed at an elevated temperature
Data Source
AI summary
The threshold voltage for vertical transistors in three-dimensional memory stack structures can be made independent of a lateral distance from a source region by forming a doped pocket region. The doped pocket region has the same conductivity type as a doped well that constitutes horizontal portions of the semiconductor channels that extend into the memory stack structures, and has a higher dopant concentration level than the doped well. The doped pocket region and a source region can be simultaneously formed by implanting p-type dopants and n-type dopants into a surface portion of the substrate underlying a backside contact trench. By selecting dopant species having different diffusion rates, the doped pocket region can surround the source region. The process parameters of the anneal process can be selected such that the interface between the dopant pocket region and the doped well underlies outermost memory stack structures.