Memory Die Stack Standby Exit via Chip-ID Wakeup Signaling
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Solution Overview
Problem
Maintaining high throughput and maximizing interface speeds in stacked memory devices is challenging due to internal connection delays, CMOS process skew, and load capacitance effects that interfere with signal transmission, particularly as the number of dies in a memory stack increases.
Innovation Solution
Implementing an intra-package bus that couples a primary die to multiple secondary dies within the memory package, using an intra-package communication protocol that enables high concurrency with reduced capacitive loading, and employing a chip ID-based command packet structure to improve manufacturing efficiency and flexibility, allowing each die to independently decide when to process commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory dies are stacked to increase memory density, then memory capacity is improved, but internal connection delays and signal transmission issues worsen
Solution Approach 1:
The patent divides the memory system into multiple independent dies (primary die and secondary dies) that can operate independently. Each die has its own command decoder and can process commands autonomously, reducing the time spent on internal connections by eliminating the need for sequential signal propagation through all dies.
Solution Approach 2:
The patent introduces an intra-package bus as an intermediary communication channel between the primary die and secondary dies. This dedicated bus provides a direct, high-speed communication path that reduces signal transmission delays compared to external package pins, enabling faster coordination between dies while maintaining independence.
2Productivity
If multiple dies are coupled to the same interface, then memory throughput can be maintained, but load capacitance effects increase and interfere with signal transmission
Solution Approach 1:
The patent segments the memory interface into a primary die interface (connected to host) and secondary die interfaces (connected via intra-package bus). This segmentation isolates the load capacitance of secondary dies from the external interface, preventing capacitance accumulation while maintaining high throughput through parallel die operations.
Solution Approach 2:
The patent moves secondary die connections from the external package dimension to an internal dimension via the intra-package bus. This dimensional shift places secondary dies closer to the primary die, reducing signal path length and minimizing capacitive loading effects on external interface signals while preserving memory throughput.
3Use of energy by moving object
If standby exit procedures are simplified for low-power operation, then power consumption is reduced, but wakeup response time increases
Solution Approach 1:
The patent implements preliminary action by continuously sampling the command line in receiver circuitry even during standby mode. This allows the system to detect wakeup commands immediately upon arrival, eliminating wake-up latency while keeping the majority of the memory device in a low-power state. The command decoder is pre-positioned to instantly recognize and respond to standby exit commands.
Data Source
AI summary
A memory device standby procedure can include idling a first memory device in a low-power standby mode, the first memory device coupled to a memory interface that couples multiple memory devices to a host and includes a command line (CA) and a standby exit line (EX), and the first memory device can include a primary die coupled to multiple secondary dies using an intra-package bus. At the first memory device, the procedure can include waking receiver circuitry on the primary die in response to a state change on the standby exit line, and sampling the command line using logic circuitry on the primary die. When a wakeup message on the command line comprises a chip identification that corresponds to the first memory device, the procedure can include initiating a standby exit procedure for the first memory device.