3D Memory Structure with Stair Contact Regions for RC Delay Reduction
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Solution Overview
Problem
Current 3D memory structures face challenges in reducing RC delay, manufacturing complexity, and cost while maintaining performance and efficiency.
Innovation Solution
The memory structure incorporates M array regions and N contact regions, where N ≥ M, with each contact region featuring a stair structure of alternately stacked conductive and insulating layers, allowing for spatial separation and electrical connection of adjacent array regions, thereby reducing word line resistance and capacitance, and utilizing symmetrical contact region placement for cost-effective manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional 3D memory structures are used, then manufacturing processes become complex and costly, but RC delay and overhead time cannot be sufficiently reduced
Solution Approach 1:
The memory structure is divided into M array regions and N contact regions, with each array region independently coupled to contact regions. This segmentation allows for reduced RC delay by shortening word line lengths while maintaining manufacturing feasibility through modular construction
Solution Approach 2:
The patent transitions from planar 2D memory structures to three-dimensional structures with vertical stacking of conductive and insulating layers forming stair structures. This dimensional change increases storage density without proportionally increasing RC delay, as the vertical arrangement shortens horizontal current paths
2Loss of energy
If more contact regions are added to reduce RC delay, then manufacturing complexity increases
Solution Approach 1:
The structure uses N contact regions where N ≥ M, creating an asymmetric configuration that optimizes electrical performance by providing multiple contact points per array region. This asymmetry reduces power consumption through lowered resistance while the standardized stair structure maintains manufacturing ease
Solution Approach 2:
The patent changes the parameter of contact region count from the conventional 1:1 ratio with array regions to N ≥ M, where each array region couples to multiple contact regions. This parameter change reduces word line resistance and power consumption while the systematic arrangement keeps manufacturing manageable
3Loss of energy
If array regions are spatially separated to reduce capacitance, then device area increases
Solution Approach 1:
The patent reduces capacitance between adjacent array regions by introducing spatial separation through contact regions, while compensating for area increase through vertical stacking. The three-dimensional arrangement with alternating conductive and insulating layers provides capacitance isolation without requiring proportional horizontal area expansion
Data Source
AI summary
A memory structure is provided. The memory structure comprises M array regions and N contact regions. M is an integer ≥2. N is an integer ≥M. Each array region is coupled to at least one contact region. Each contact region comprises a stair structure and a plurality of contacts. The stair structure comprises alternately stacked conductive layers and insulating layers. Each contact is connected to one conductive layer of the stair structure. Two array regions which are adjacent to each other are spatially separated by two contact regions, which are coupled to the two array regions, respectively.