3D Memory Stair-Step Layout for Simpler Wordline Access
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Solution Overview
Problem
Current memory circuitry technologies face challenges in efficiently forming memory arrays with vertically-stacked memory cells, particularly in creating effective stair-step structures for electrical access and reducing the complexity of masking steps in the manufacturing process.
Innovation Solution
The method involves forming a stack with vertically-alternating conductive and insulative tiers, using anisotropically-etched spacers to create multiple treads per stair in the stair-step region, which simplifies the masking process and reduces the number of stair-step structures required for accessing wordlines, while ensuring direct electrical coupling of channel material to conductor tiers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional masking steps are used to form stair-step structures for electrical access, then electrical access to wordlines is achieved, but the manufacturing process complexity increases
Solution Approach 1:
The spacer structures self-align to the stair-step features during formation, automatically defining the through-array via locations without requiring additional masking steps. The spacers serve both as structural elements and as alignment references for subsequent processing
Solution Approach 2:
The spacers are formed beforehand to pre-establish the precise locations where through-array vias will be created. This preliminary positioning eliminates the need for complex masking operations during the via formation stage
2Adaptability or versatility
If multiple stair-step structures are used to access different wordline tiers, then electrical access to multiple wordlines is achieved, but the number of required structures increases
Solution Approach 1:
Each spacer structure serves multiple functions: it defines the location for a through-array via, provides structural support, and establishes alignment for multiple wordline tiers. The same spacer formation process applies to all wordline tiers, creating a universal approach rather than requiring unique structures for each tier
3Ease of manufacture
If through-array vias are formed without precise alignment, then via formation is simplified, but the risk of shorting between conductor tiers increases
Solution Approach 1:
The insulative tier acts as an intermediary barrier between adjacent conductor tiers. The spacers are formed within this insulative layer, creating physical boundaries that guide via formation and prevent direct contact between conductive elements of different tiers, thereby eliminating shorting risks while maintaining manufacturing simplicity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the efficiency of memory cell formation by simplifying the manufacturing process, reducing the risk of shorting through-array vias, and providing reliable electrical access to memory cells, thereby improving the overall performance of memory circuitry.
Implementation Method 1
First and second anisotropically-etched spacers are formed that extend along the first direction directly above the flight of stairs. The first and second anisotropically-etched spacers are used as a mask while etching there-between through one of the first tiers and one of the second tiers
Data Source
AI summary
Memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. The stair-step region comprises a flight of stairs extending along a first direction. Multiple different-depth treads in individual of the stairs extend along a second direction that is orthogonal to the first direction. Individual of the multiple different-depth treads comprise conducting material of one of the conductive tiers. The multiple different-depth treads in the individual stairs comprise in lateral-succession along the second direction a first higher-depth tread, a lower-depth tread, and a second higher-depth tread. Methods are also disclosed.