3D Memory Staircase Layout With Sub-Staircases to Shorten Word-Line Leadout
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Solution Overview
Problem
In three-dimensional nonvolatile memory manufacturing, the staircase structure used to lead out stacked word lines requires a large number of processing steps, increasing manufacturing complexity and staircase length, which is undesirable.
Innovation Solution
The semiconductor storage device employs a staircase portion with multiple sub-staircase portions that are processed to different levels using a multi-stage lowering technique, allowing for reduced staircase length by optimizing mask pattern alignment and etching margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If a traditional staircase structure is used to lead out stacked word lines, then the conductive layers can be successfully led out, but the staircase length becomes too long and manufacturing complexity increases
Solution Approach 1:
The staircase structure is divided into multiple sub-staircase portions (first, second, third sub-staircase portions) with different numbers of steps. This segmentation allows each portion to be optimized independently, reducing the overall staircase length while maintaining the functionality of leading out multiple word lines.
Solution Approach 2:
Different regions of the staircase structure are assigned different characteristics. The first sub-staircase portion has a different number of steps compared to the second and third portions, creating local variations that optimize the overall structure for reduced length and simplified manufacturing in different areas.
2Manufacturing precision
If the number of processing steps is increased to create the staircase structure, then the staircase portion can be formed, but manufacturing complexity and time increase
Solution Approach 1:
Multiple etching processes are combined into a single multi-step etching operation. The etching process simultaneously creates different numbers of steps in different sub-staircase portions by using a single mask pattern, thereby reducing the total number of processing steps required while maintaining precise staircase structure formation.
Solution Approach 2:
A mask pattern is formed in advance that defines the entire staircase structure including all sub-staircase portions with different step counts. This preliminary mask formation allows subsequent etching to create the complex multi-level structure in one operation rather than requiring multiple separate processing steps.
Data Source
AI summary
A semiconductor storage device according to an embodiment includes: a stacked body in which a plurality of conductive layers are stacked via an insulating layer and which has a memory region in which a plurality of memory cells are disposed and a staircase region in which end portions of the plurality of conductive layers form a staircase shape. A first region of the staircase region includes a first sub-staircase portion ascending in a first direction toward the memory portion, and a second sub-staircase portion disposed side by side with the first sub-staircase portion in a second direction opposite to the first direction from the first sub-staircase portion and ascending in the second direction.