Memory Status Memory Row Block Repair Control
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Solution Overview
Problem
Existing memory integrated circuits face inefficiencies in defect repair due to the need for additional redundant columns and increased storage of repair status information when dividing columns into multiple row blocks, which complicates the verification process and consumes area.
Innovation Solution
An integrated circuit design that divides main columns and redundant columns into row blocks, with status memory and control circuitry updating repair statuses only for a subset of row blocks accessed by a command, excluding repaired columns from the verify procedure and performing updates during memory operation voltage setup to minimize latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If columns are divided into multiple row blocks to improve area efficiency of redundant columns, then area efficiency is improved, but the volume of repair status information that must be stored increases
Solution Approach 1:
The patent divides the memory array into multiple row blocks (first row blocks, second row blocks, etc.) and segments the repair status tracking by maintaining separate status information for each row block type. This allows the system to track repairs at a granular level without requiring comprehensive status information for all possible column combinations, thereby reducing the overall volume of status memory required while maintaining area efficiency through the row block division approach.
2Reliability
If more redundant columns are added to address defects in different columns, then defect repair capability is improved, but area consumption increases
Solution Approach 1:
The patent implements a unified repair mechanism where a single redundant column can serve multiple main columns by replacing row blocks in different row blocks. The control circuitry determines whether to perform repairs based on row block type and repair status, allowing one redundant column to functionally replace multiple defective columns across different row blocks, thereby improving defect repair capability without proportionally increasing the number of redundant columns required.
3Measurement precision
If repair statuses for all row blocks are stored to enable complete verification, then verification accuracy is improved, but status memory size increases
Solution Approach 1:
The patent applies local quality by maintaining repair status information specifically for accessed row blocks rather than all row blocks uniformly. The control circuitry updates status memory only for the subset of row blocks that are accessed during a particular operation, and verification is performed only on repaired row blocks within the accessed subset. This localized approach ensures verification accuracy for relevant operations while minimizing status memory size by not storing redundant status information for unaccessed row blocks.
Data Source
AI summary
An integrated circuit includes an array of memory cells that is arranged into rows, main columns, and redundant columns that perform repairs in the array. The main columns and the redundant columns are divided into row blocks. Bit lines couple the main columns to status memory indicating repair statuses of the repairs by the redundant columns. The integrated circuit receives a command, and performs an update on the status memory with the repair statuses specific to particular ones of the row blocks in a portion of the memory accessed by the command. Alternatively or in combination, the status memory has insufficient size to store the repair statuses of multiple ones of the row blocks of the main columns.