Semiconductor Memory Step Structure Spacer Isolation
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Solution Overview
Problem
The miniaturization of semiconductor memory devices requires precise process control to achieve a step-shaped structure for three-dimensional nonvolatile memories, which is challenging due to the difficulty in obtaining sufficient process margins.
Innovation Solution
A semiconductor memory device with a stack body featuring a step structure comprising alternately stacked wire line layers and interlayer insulating layers, where lead wire lines are used to connect the lowermost wire line layer of one step to the terrace portion of a lower step, with spacers covering the step portions to prevent electrical connection between adjacent wire lines, allowing for increased thickness of lead wire lines without precise process control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a step-shaped structure is adopted to lead out word lines in three-dimensional nonvolatile memory, then the memory device can be miniaturized and stacked in height direction, but precise process control becomes difficult and sufficient process margin cannot be obtained
Solution Approach 1:
A spacer layer is introduced as an intermediary element between the first and second wire line layers. This spacer serves as a physical barrier that prevents electrical conduction between adjacent wire lines while allowing the lead wire line to be thicker. The spacer mediates the interaction between adjacent conductive layers, enabling miniaturization without requiring precise process control for thin wire lines.
Solution Approach 2:
The structure is segmented into distinct functional layers: a first wire line layer, a spacer layer, and a second wire line layer. This segmentation allows each layer to be optimized independently - the lead wire line can be made thicker for manufacturability while the spacer provides electrical isolation, resolving the contradiction between miniaturization and manufacturing precision.
2Reliability
If the thickness of lead wire line is increased to enhance manufacturing reliability, then manufacturing efficiency improves, but electrical conduction between adjacent wire lines may occur
Solution Approach 1:
The spacer layer acts as an intermediary barrier that physically separates the first and second wire line layers. This allows the lead wire line to have increased thickness for improved manufacturing reliability and electrical conductivity, while the spacer prevents harmful electrical conduction between adjacent wire lines by providing electrical isolation.
Solution Approach 2:
The structure exhibits local quality differentiation: the lead wire line has increased thickness in regions where electrical conductivity is desired, while the spacer layer provides thin electrical isolation in regions where conduction prevention is needed. This local differentiation resolves the contradiction between reliability and harmful electrical conduction.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes: a stack body having a step structure body with a plurality of wire line layers and a plurality of interlayer insulating layers alternately stacked being set as one step on a substrate; and memory cells arranged three-dimensionally in the stack body, in which the step structure body includes: a plurality of terrace portions configured with the interlayer insulating layers, the plurality of terrace portions having different heights; a plurality of step portions connecting the respective terrace portions in a height direction; insulating layers covering the step portions; and a lead wire line leading out a lowermost wire line layer of a first step onto the terrace portion of a second step being a lower step of the first step.