3D Memory String Integrated Semiconductor Layers
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in miniaturization due to increasing costs and physical limitations, such as high contact resistance between columnar semiconductors, which affects device reliability and operation.
Innovation Solution
A nonvolatile semiconductor memory device with a configuration of memory strings and select transistors featuring integrated semiconductor and insulating layers, along with charge storage layers, to reduce contact resistance and enhance reliability, including the use of U-shaped semiconductor layers and continuous layer formation to stabilize transistor characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If columnar semiconductors are formed in separate processes and then joined, then integration density can be increased, but contact resistance arises between the columnar semiconductors leading to incorrect operation
Solution Approach 1:
The patent merges the formation of first and second columnar semiconductors into a single continuous process. The semiconductor layer is formed continuously to simultaneously create both columnar semiconductors and the in-between semiconductor, eliminating the need for separate processes and joining operations. This integration reduces contact resistance while maintaining high integration density.
Solution Approach 2:
The patent introduces an in-between semiconductor as an intermediary element connecting the first and second columnar semiconductors. This in-between semiconductor is formed simultaneously with the columnar semiconductors in a continuous process, providing a reliable conductive path that eliminates contact resistance issues associated with joined structures.
2Ease of manufacture
If interface treatment is performed in solution containing dilute hydrofluoric acid to connect columnar semiconductors, then connection between upper and lower columnar semiconductors is achieved, but memory gate insulating layer may be damaged
Solution Approach 1:
The patent performs preliminary action by forming the in-between semiconductor simultaneously with the columnar semiconductors in a continuous formation process. This eliminates the need for subsequent interface treatment with hydrofluoric acid, thereby preventing damage to the memory gate insulating layer while achieving reliable connection between semiconductor structures.
3Productivity
If miniaturization is pursued to increase storage capacity, then element dimensions are reduced, but physical limitations such as withstand voltage between elements are encountered
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional vertical stacking. Multiple memory cells are stacked in the vertical direction above a single bit line, allowing increased storage capacity without reducing element dimensions. This dimensional change maintains adequate withstand voltage between elements while achieving higher density.
Data Source
AI summary
A memory string comprises: a pair of columnar portions; a first insulating layer surrounding a side surface of the columnar portions; a charge storage layer surrounding a side surface of the first insulating layer; a second insulating layer surrounding a side surface of the charge storage layer; and a first conductive layer surrounding a side surface of the second insulating layer. A select transistor comprises: a second semiconductor layer extending from an upper surface of the columnar portions; a third insulating layer surrounding a side surface of the second semiconductor layer; a fourth insulating layer surrounding a side surface of the third insulating layer; and a second conductive layer surrounding a side surface of the fourth insulating layer. The first semiconductor layer is formed continuously in an integrated manner with the second semiconductor layer. The first insulating layer is formed continuously in an integrated manner with the third insulating layer.