Memory Device Sub-Array Multiplexing for Defect Repair
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Solution Overview
Problem
High-capacity memory devices often suffer from failed memory cells due to fine process technologies, leading to reduced yield and storage capacity issues, as manufacturers struggle to effectively utilize extra storage capacity and repair defective cells.
Innovation Solution
A memory device design incorporating multiple sub-memory cell arrays, a multiplexing circuit, and a control logic circuit that selectively connects these arrays to input/output pads based on operating modes, allowing for the use of extra capacity as a repair area or providing additional storage, thereby compensating for defective cells and optimizing storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fine process technology is used to manufacture high-capacity memory devices, then storage capacity increases, but the number of failed memory cells increases
Solution Approach 1:
The memory device is divided into multiple independent sub-memory cell arrays (first, second, third sub arrays). This segmentation allows the system to isolate defective cells within specific sub-arrays while maintaining functionality of other sub-arrays, thereby preserving overall storage capacity despite process-induced failures.
Solution Approach 2:
The system dynamically changes operational parameters by switching between different modes (first mode utilizing all sub-arrays, second mode utilizing only non-defective sub-arrays) based on the detected status of memory cells. This parameter change allows the device to adapt to failures while maintaining optimal performance.
2Productivity
If extra storage capacity is added to compensate for defective cells, then yield improves, but device complexity increases
Solution Approach 1:
The third sub-memory cell array serves multiple functions: it acts as extra storage capacity in the first mode and as a repair area in the second mode when defective cells are detected in the first or second sub-arrays. This multi-functionality allows the same hardware resource to address both storage capacity and yield improvement needs without adding separate dedicated repair structures.
Solution Approach 2:
The system employs dynamic reconfiguration through a multiplexing circuit and control logic that can switch between different operational modes. The multiplexing circuit dynamically connects different sub-arrays to input/output pads based on the detected defect status, enabling the device to adapt its internal configuration without physical changes or external intervention.
3Ease of repair
If multiple sub-memory cell arrays are implemented with multiplexing circuits, then defective cell repair capability improves, but manufacturing complexity increases
Solution Approach 1:
The multiplexing circuit combines the control of multiple sub-memory cell arrays into a unified structure that selects which arrays connect to the shared input/output pads. By merging the connection control functionality into a single multiplexing unit rather than providing separate dedicated paths for each sub-array, the design reduces the overall number of connections and simplifies manufacturing while maintaining the ability to isolate and repair defective cells.
Data Source
AI summary
A memory device includes a memory cell array, a multiplexing circuit, and a control logic circuit. The memory cell array includes a first sub memory cell array, a second sub memory cell array, and a third sub memory cell array. The multiplexing circuit selects the first sub memory cell array, the second sub memory cell array, and the third sub memory cell array in a first mode of operation, and when the first sub memory cell array is defective in a second mode of operation, the multiplexing circuit selects the second sub memory cell array and the third sub memory cell array. The control logic circuit selects the first mode of operation or the second mode of operation. The control logic circuit controls the multiplexing circuit so that the first, second and third sub memory cell arrays are connected to input or output pads.