3D Nonvolatile Memory Sub-Block Erase Voltage Control
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Solution Overview
Problem
Conventional three-dimensional semiconductor memory devices face challenges in selectively erasing memory cells within a memory block due to increased complexity and capacitive coupling issues as the number of layers and word lines grows, making it difficult to perform efficient erase operations.
Innovation Solution
The nonvolatile semiconductor memory device employs a control circuit that applies specific voltages to bit lines, source lines, and select gate lines to selectively erase memory blocks by generating a potential difference, preventing false erase operations in unselected blocks through the use of sub-blocks and select gate lines with distinct voltage configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are disposed three-dimensionally to increase integration degree, then storage capacity is improved, but capacitive coupling between memory elements increases causing operation difficulty
Solution Approach 1:
The memory block is divided into multiple sub-blocks, with each sub-block containing a specific number of memory strings connected to shared word lines. This segmentation allows selective erase operations to be performed on individual sub-blocks, isolating the capacitive coupling effects to smaller groups of memory elements and enabling precise control during erase operations.
2Quantity of substance
If the number of layers and word lines is increased to expand memory capacity, then storage capacity is improved, but complexity of selective erase operations increases
Solution Approach 1:
By organizing memory strings into sub-blocks that share common word lines, the patent creates a hierarchical structure where erase operations can be selectively applied to specific sub-blocks. This reduces the complexity of selective erase operations compared to managing individual memory strings or entire memory blocks, as the sub-block structure provides a manageable intermediate level of organization.
Solution Approach 2:
Different voltage configurations are applied to different sub-blocks during erase operations. Selected sub-blocks receive voltage combinations that enable erase, while unselected sub-blocks receive voltage configurations that prevent false erase. This local differentiation of voltage application simplifies the control logic for selective erase operations in large-capacity three-dimensional memory.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for precise and efficient erase operations on a sub-block basis within a memory block, reducing the risk of false erasures and improving the operational reliability of the memory device by managing capacitive coupling and voltage differences effectively.
Implementation Method 1
a control circuit configured to apply a first voltage to the bit lines and the source line, and a second voltage smaller than the first voltage to the word lines for execution of an erase operation in a selected sub-block
Data Source
AI summary
When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.