Memory Subsystem Weak Bit Detection for Refresh Rate Optimization
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Solution Overview
Problem
Existing memory devices often default to standard refresh frequencies, which can lead to inefficiencies in power usage and performance, as they do not account for variations in memory cell reliability within the device, resulting in some cells being weaker and affecting overall system performance.
Innovation Solution
A test engine embedded within the memory subsystem performs in-system testing to identify weak bits or lines that produce errors at lower refresh rates, allowing these to be mapped out, thereby adjusting the refresh rate to optimize performance and reduce power consumption by extending the refresh cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory devices operate at standard refresh frequencies, then reliability is maintained, but power consumption increases and performance is limited
Solution Approach 1:
The patent applies local quality by differentiating between weak bits and strong bits within the memory device. Weak bits are identified through in-system testing and assigned a higher refresh rate to maintain data retention, while strong bits operate at a lower refresh rate to reduce power consumption. This localized differentiation allows the system to optimize power usage without compromising the reliability of vulnerable memory locations.
Solution Approach 2:
The patent implements dynamics by making the refresh rate adjustable and adaptive rather than fixed. The system dynamically determines the refresh rate based on in-system testing results, allowing memory locations to operate at different refresh rates according to their individual reliability characteristics. This dynamic approach enables the memory device to optimize between power consumption and reliability based on actual performance data.
2Use of energy by moving object
If memory devices use lower refresh rates, then power consumption decreases, but errors occur in weak bits
Solution Approach 1:
The patent applies preliminary action by performing in-system testing during the manufacturing or initialization phase to identify weak bits before the memory device enters normal operation. This advance identification allows the system to establish appropriate refresh rates for each memory location beforehand, ensuring that weak bits are protected against errors while strong bits operate efficiently at lower refresh rates.
Solution Approach 2:
The patent differentiates between weak bits and strong bits, applying different refresh rates to different locations based on their individual characteristics. Weak bits receive higher refresh rates to prevent errors, while strong bits operate at lower refresh rates to minimize power consumption. This localized quality approach ensures that reliability is maintained only where necessary.
3Reliability
If memory devices are tested prior to production, then minimum performance expectations are verified, but in-system variations and weak bits are not identified
Solution Approach 1:
The patent performs in-system testing during the initialization phase, which is a preliminary action taken before normal operation begins. This testing identifies weak bits that may not be detected during traditional pre-production testing, allowing the system to adapt refresh rates based on actual in-system performance characteristics.
Solution Approach 2:
The patent implements feedback by using the results of in-system testing to adjust and optimize the refresh rate configuration. The testing provides feedback about actual memory location performance, which is then used to configure appropriate refresh rates, creating a closed-loop system that adapts to in-system variations.
4Device complexity
If all memory locations are refreshed at the same rate, then simplicity is maintained, but power efficiency is reduced due to unnecessary refreshing of strong bits
Solution Approach 1:
The patent applies local quality by assigning different refresh rates to different memory locations based on their individual characteristics. Strong bits are identified and assigned lower refresh rates to reduce unnecessary power consumption, while weak bits receive higher refresh rates to maintain reliability. This localized differentiation eliminates wasted energy on already-reliable memory locations.
Solution Approach 2:
The patent segments the memory device into different categories of memory locations (weak bits and strong bits) based on in-system testing results. This segmentation allows the system to apply different refresh rate policies to different segments, optimizing power consumption without requiring complex per-bit management during normal operation.
Data Source
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AI summary
A memory subsystem can test a memory device in situ, testing the performance of the device in the system it is built into during production. Thus, the refresh rate can be adjusted specific to the memory device(s) of a specific system, rather than defaulting to a refresh frequency specified by a standard for the memory device(s). A test component embedded within the host memory subsystem can perform a test and identify specific bits or lines of memory that produce errors when a lower frequency refresh rate is used. The system maps out the identified bits or lines to prevent the bits/lines from being used in runtime of the system. The memory subsystem can then set its refresh rate to an adjusted refresh rate at which a threshold number of errors can be removed by mapping out the bits/lines.