Memory Device Switch Circuit Configuration for Resistance Variation
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Solution Overview
Problem
Current memory devices using variable resistance elements face challenges in efficiently managing interconnect resistance variations across different areas of the memory cell array, leading to potential malfunctions and reduced reliability due to varying coordinates of memory cells.
Innovation Solution
The memory device employs a configuration with multiple switch circuits (column and row switch circuits) that activate differently based on the coordinates of the selected memory cell, optimizing interconnect resistance by connecting memory cells to global bit and word lines through specific switch circuit combinations, thereby reducing the impact of resistance variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are distributed across a large memory cell array, then the storage capacity increases, but the interconnect resistance variations increase leading to malfunctions
Solution Approach 1:
The memory cell array is divided into multiple areas with different interconnect resistance characteristics. Switch circuits are strategically placed at different locations (first switch circuit at first area, second switch circuit at second area) to segment the large array into manageable zones. This segmentation allows the system to handle resistance variations in different regions independently, maintaining reliability while preserving large storage capacity.
Solution Approach 2:
Different switch circuits are positioned at different locations within the memory cell array to address local resistance characteristics. The first switch circuit serves the first area while the second switch circuit serves the second area, allowing each local region to be optimized for its specific interconnect resistance properties. This local quality approach ensures that memory cells throughout the entire array, regardless of location, can operate reliably.
2Reliability
If switch circuits are added to manage resistance variations, then the reliability improves, but the device complexity increases
Solution Approach 1:
Switch circuits are extracted and placed at specific strategic locations (first area and second area) within the memory cell array rather than distributing them uniformly or placing them only at the periphery. This extraction approach allows the system to address resistance variations with minimal switch circuits positioned where they are most needed, improving reliability without unnecessarily increasing overall device complexity.
Solution Approach 2:
The switch circuits serve multiple functions: they act as selection switches for memory cell access and simultaneously compensate for interconnect resistance variations in their respective areas. By making the switch circuits multi-functional, the patent improves reliability against resistance variations without adding dedicated compensation circuits, thereby avoiding excessive complexity increase.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the likelihood of malfunctions and improves the reliability of memory operations by minimizing the effect of interconnect resistance differences across the memory cell array, enhancing the overall performance of the memory device.
Implementation Method 1
A memory device using a variable resistance element (for example, a magnetoresistive effect element) as a memory element is known.
Data Source
AI summary
According to one embodiment, a memory device includes: a memory cell array including first to ninth areas; first and second column switch circuits; first and second row switch circuits. In a case where a cell in the sixth area is selected, the first and second column switch circuits and the first row switch circuit are activated, and in a case where a cell in the seventh area is selected, the second column switch circuit and the first and second row switch circuits are activated, and in a case where a cell in the eighth area is selected, the first and second column switch circuits and the second row switch circuit are activated, and in a case where a cell in the ninth area is selected, the first column switch circuit and the first and second row switch circuits are activated.