Memory System Dynamic Read Level Adjustment
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Solution Overview
Problem
Existing memory systems face challenges in accurately reading data from NAND flash memory due to errors caused by threshold voltage distribution shifts, leading to incorrect data retrieval and failure in error correction processes.
Innovation Solution
A memory system with a voltage correction circuit that calculates and adjusts read levels by comparing pre-error correction and post-error correction data, using a voltage information table to determine suitable read levels for accurate data retrieval, even in cases of errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional fixed read levels are used for reading data from NAND flash memory, then the reading process is simple and fast, but data retrieval accuracy deteriorates due to threshold voltage distribution shifts causing read errors
Solution Approach 1:
The patent implements dynamic read level adjustment by storing multiple read level values in a voltage information table and selecting appropriate read levels based on the physical address of the memory block being read. This allows the read level to adapt to threshold voltage distribution shifts that occur during memory operation, thereby maintaining data retrieval accuracy without requiring complex real-time measurement and adjustment circuits.
Solution Approach 2:
The patent performs preliminary classification of memory blocks into different regions (first region with higher threshold voltage shift and second region with lower shift) and pre-calculates appropriate read level values for each region before actual data reading operations. This preliminary action enables the system to compensate for threshold voltage shifts proactively, improving read accuracy without adding complexity to the actual reading process.
2Measurement precision
If read levels are adjusted to compensate for threshold voltage distribution shifts, then data retrieval accuracy improves, but the time required for data reading increases due to additional correction processes
Solution Approach 1:
The patent pre-calculates and stores optimal read level values for different memory block regions in a voltage information table during manufacturing or initial operation. This preliminary action eliminates the need for time-consuming real-time calculations or measurements during actual data reading operations, thereby maintaining high read accuracy while minimizing additional time overhead.
Solution Approach 2:
The patent applies different read level values to different memory block regions based on their specific threshold voltage characteristics. By classifying memory blocks into regions with different shift characteristics and applying localized read level corrections only where needed, the system achieves high read accuracy without uniformly increasing reading time across all memory operations.
3Reliability
If multiple read level values are stored and selected based on memory block regions, then read error correction capability improves, but memory system complexity increases due to additional management structures
Solution Approach 1:
The patent segments the memory system into different block regions (first region and second region) with distinct threshold voltage shift characteristics and assigns different read level values to each segment. This segmentation allows the system to manage complexity by treating different regions independently with simplified, region-specific read level parameters rather than requiring a complex unified adjustment mechanism for the entire memory.
Solution Approach 2:
The voltage information table serves multiple functions: it stores read level values for different memory block regions, acts as a lookup table for rapid read level selection, and provides a structured mechanism for managing threshold voltage compensation. This multi-functionality reduces overall system complexity by consolidating multiple management tasks into a single unified data structure.
Data Source
AI summary
According to one embodiment, a memory system includes: a controller configured to execute an error correction process on first data read from a first area at a first address of a memory device and determine a read level used for reading data at the first address according to a result of the correction process. The controller executes the correction process on first frame data of the first data. When the correction process on the first frame data has failed, the controller executes the correction process on second frame data of the first data. When the correction process on the second frame data has succeeded, the controller determines the read level based on a result of comparison between the second frame data and a result of the correction process on the second frame data.