Memory Tag Comparison Circuit Layout Optimization
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Solution Overview
Problem
Conventional dynamic random access memory (DRAM) tag comparison circuits require a large layout area due to the use of multiple transistors for XOR gates, increasing costs.
Innovation Solution
The memory apparatus employs a first comparison circuit and multiple second comparison circuits, each coupled to sense amplifiers, to compare data signals with tags, reducing the number of transistors needed and optimizing layout efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional XOR gates with 6-8 transistors are used for tag comparison, then comparison functionality is achieved, but layout area increases and cost increases
Solution Approach 1:
The patent extracts the comparison functionality from conventional XOR gate structures and implements it using a simplified circuit architecture that uses sense amplifiers and cross-coupled transistors, removing the need for 6-8 transistors per comparison operation
Solution Approach 2:
The patent changes the structural parameters of the comparison circuit by transitioning from a transistor-intensive XOR gate design to a sense amplifier-based design with cross-coupled transistors, fundamentally altering the circuit topology to reduce area
2Reliability
If conventional XOR gates with 6-8 transistors are used for tag comparison, then comparison functionality is achieved, but cost increases
Solution Approach 1:
The patent extracts the comparison functionality from expensive XOR gate structures and implements it using a more cost-effective circuit architecture with fewer transistors, directly reducing manufacturing costs
Solution Approach 2:
The patent employs a simplified comparison circuit design that uses fewer transistors and less complex structures, creating a more economical solution that is easier and cheaper to manufacture
Data Source
AI summary
The present disclosure provides a memory apparatus including a memory cell array, a plurality of sense amplifiers, at least one first comparing circuit, and a plurality of second comparing circuit. The memory cell array includes a plurality of memory cells. Each of the sense amplifier generates a data signal and an inverted data signal according to a bit line signal and an inverted bit line signal. The first comparing circuits compares the data signals of first and second sense amplifiers with a first tag to generate a first comparing result. The second comparing circuits respectively compare a plurality of second tags with the data signals of the sense amplifiers to respectively generate a plurality of second comparing results.