Memory Test Circuit Using Address Lines for Data Input
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Solution Overview
Problem
The increasing number of integrated chips on a wafer in semiconductor fabrication leads to a significant increase in the time and cost of wafer-level testing due to the need for a large number of signal channels in test machines, limiting the effectiveness of parallel testing methods.
Innovation Solution
A circuit and method for testing memory devices that generate write and read test vectors using address lines, allowing for comparison with readout signals to produce a flag indicative of test results, reducing the need for data channels and enabling more parallel testing without increasing test machine resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallel test method is used to test multiple chips simultaneously, then testing productivity is improved, but the number of signal channels required increases significantly
Solution Approach 1:
The patent merges the test data input function with the existing address lines by using them as data input channels. The test pattern generator uses address lines to carry test data, eliminating the need for separate data input channels. This combining approach allows multiple chips to be tested in parallel without proportionally increasing the number of signal channels required in the test machine.
Solution Approach 2:
The address lines are given multiple functions: they serve both as address signals for memory access and as data input channels for test patterns. This multi-functionality reduces the total number of dedicated signal channels needed, enabling higher parallel testing capacity without proportional increases in test machine complexity.
2Productivity
If the number of chips integrated on a wafer is increased, then manufacturing efficiency is improved, but the testing time and cost increase significantly
Solution Approach 1:
The patent segments the testing process into independent testable units where each chip can be tested simultaneously using the same reduced signal channel infrastructure. By segmenting the test architecture to work with individual chip test patterns generated from address lines, the system can scale the number of chips tested in parallel without linearly increasing testing time or cost.
Solution Approach 2:
The patent changes the parameter usage of address lines from solely address signaling to dual-purpose address and data input signaling. This parameter change enables the test machine to maintain a fixed number of signal channels while testing an increasing number of chips in parallel, thereby reducing testing time per chip and overall testing cost as wafer capacity increases.
3Reliability
If data lines are connected to independent signal channels for parallel testing, then test accuracy is improved, but the cost of the test machine increases
Solution Approach 1:
The patent combines multiple data line connections into a single shared signal channel infrastructure by using address lines as data input carriers. This merging maintains test accuracy by preserving the ability to input test patterns to each memory device while significantly reducing the number of independent signal channels required, thereby lowering test machine cost.
Solution Approach 2:
The patent uses the existing address line signal paths as copies or substitutes for dedicated data input channels. By copying the function of data input onto the address line infrastructure, the system achieves equivalent test capability without requiring separate physical channels, thus reducing test machine complexity and cost.
Data Source
AI summary
The present application provides a circuit and method for testing a memory device. The memory device has multiple blocks addressable via a plurality of address lines and capable of inputting and/or outputting data via a plurality of data lines. The circuit comprises: a test pattern generator coupled to a first portion of the plurality of address lines to receive test data, and configured to store the test data and to generate a write test vector and a read test vector according to the test data, wherein the write test vector is associated with the read test vector; a multiplexer coupled to the test pattern generator, and configured to selectively transmit the write test vector to a subject block of the multiple memory blocks to enable the write test vector to be written into the subject block; and a comparator coupled to the test pattern generator and the subject block, and configured to compare the read test vector with a readout signal generated from the subject block and the write test vector, and to generate a flag indicative of the comparison result.