Memory Test Circuit With Embedded High-Speed BIST
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory testing methods are limited by the interface frequencies of the memory chip, hindering high-speed testing of memory devices.
Innovation Solution
A build-in self-test (BIST) circuit is embedded within the memory chip to generate high-frequency test signals for memory testing, comprising a high speed clock, finite state machine controller, pattern generator, and output comparator, allowing for high-speed memory testing without interface constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If external interface testing is used, then testing can be performed, but the testing speed is limited by interface frequency
Solution Approach 1:
The memory chip performs self-testing through an embedded BIST circuit that generates test signals internally and compares readout signals with expected results, eliminating dependence on external testing interfaces and their frequency limitations
Solution Approach 2:
The test circuit is merged with the memory chip structure, integrating the pattern generator, comparator, and control logic within the chip itself to enable autonomous high-speed testing
2Productivity
If external testing interface is used, then memory testing can be performed, but high-speed testing is hindered
Solution Approach 1:
The memory chip autonomously generates test patterns and evaluates results through embedded BIST circuitry, eliminating the need for external testing equipment and interface protocols that constrain testing speed and efficiency
Data Source
AI summary
A memory test circuit is provided. The memory test circuit is disposed in a memory chip and electrically coupled to a memory macro of the memory chip. A high speed clock receives an input signal and an external clock signal. The input signal includes a plurality of test bits. A finite state machine controller provides a pattern type. A pattern generator generates and provides a test signal to at least one memory cell of the memory chip to write the test signal to the at least one memory cell based on the pattern type and the external clock signal. A test frequency of the test signal is determined based on the high speed clock. An output comparator outputs a comparison signal based on a difference between the test signal and a readout signal corresponding to the test signal read from the at least one memory cell.