Memory Test Circuit Repair Information Storage Mechanism
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Solution Overview
Problem
During scan testing of memory chips, data loss in shift registers can prevent accurate repair of memory faults, leading to false test results and incomplete repair of defective memory circuits.
Innovation Solution
A memory test circuit with a built-in self-repair mechanism, including a remapping storage circuit and a latch storage circuit, which stores and maintains repairing information generated by the memory built-in self-repair circuit, allowing for accurate remapping and repair of memory circuits with redundant structures during scan testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shift registers in the scan chain are used to store repairing information, then the memory can be tested for faults, but data loss occurs during shifting operation causing inaccurate repair
Solution Approach 1:
The patent introduces a dedicated repairing information storage circuit as an intermediary component between the MBISR circuit and the remapping circuit. This separate storage circuit holds the repairing information stable during scan testing, preventing data loss while maintaining the ability to perform accurate repairs. The intermediary storage acts as a buffer that decouples the shifting operation from the repairing information preservation.
2Productivity
If the remapping storage circuit is disposed in the scan chain, then scan testing can be performed, but repairing information may be lost during shifting
Solution Approach 1:
The patent segments the storage function by separating the repairing information storage from the general scan chain functionality. The remapping storage circuit is divided into a first storage portion for repairing information and a second storage portion for scan test data. This segmentation allows the scan chain to perform its testing function while the dedicated first storage portion maintains repairing information stable and protected from shifting operations.
3Device complexity
If repairing information is stored in the scan chain registers, then the circuit structure is simplified, but the memory cannot be accurately repaired
Solution Approach 1:
The patent introduces a dedicated repairing information storage circuit as an intermediary component between the MBISR circuit and the remapping circuit. This separate storage circuit holds the repairing information stable during scan testing, preventing data loss while maintaining the ability to perform accurate repairs. The intermediary storage acts as a buffer that decouples the shifting operation from the repairing information preservation.
Solution Approach 2:
The patent performs preliminary storage of repairing information in a dedicated stable storage location before the scan testing process begins. By pre-storing the repairing information in the remapping storage circuit's first storage portion, the system ensures that this critical data is preserved and protected from the subsequent shifting operations that occur during scan testing, thereby maintaining repair accuracy.
Data Source
AI summary
The present invention discloses a memory test circuit having repair information maintaining mechanism. A repairing control circuit controls a MBISR circuit to perform a self-repair procedure on a memory circuit and includes a remapping storage circuit and a latch storage circuit. The remapping storage circuit receives and stores repairing information generated by the MBISR circuit after the self-repair procedure finishes. The latch storage circuit is electrically coupled between the remapping storage circuit and a remapping circuit corresponding to the memory circuit to receive and store the repairing information from the remapping storage circuit such that the remapping circuit accesses the repairing information therefrom when a scan test is performed on the remapping storage circuit based on a scan chain to perform remapping and repairing on the memory circuit based on the repairing information and a redundant structure of the memory circuit.