Semiconductor Memory Test Circuit Voltage Stabilization

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Solution Overview

Problem

The testing time for semiconductor memory devices is increased due to sudden fluctuations in power supply voltage caused by changes in current consumption during the transition from a standby mode to a write or read mode, resulting from parasitic resistance, inductance, and capacitance components in the power lines.

Innovation Solution

A test circuit that generates a leakage current equal to the operating current during a standby state when activated, minimizing current differences and stabilizing the voltage by including a current sink unit and a current sink enable signal generating unit, which receive a test mode signal and a standby signal to manage the current flow.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the semiconductor memory device transitions from standby mode to write or read mode, then the device becomes operational, but sudden voltage fluctuations occur due to parasitic resistance, inductance, and capacitance components in the power lines

Engineering Contradiction:
Improvetest speedVSAvoidvoltage stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The test circuit generates leakage current in advance during the standby state before the actual write or read operation begins. This preliminary action ensures that the current consumption is already at the operational level when the mode transition occurs, preventing sudden voltage fluctuations and allowing immediate testing without waiting for voltage stabilization.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The invention changes the current consumption parameter during the standby state by activating the test circuit to generate leakage current equal to the operational current. This parameter change from low standby current to high leakage current mimics the operational current profile, thereby stabilizing the voltage during mode transitions and enabling faster testing.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the test circuit generates leakage current equal to operating current during standby state, then voltage fluctuations are minimized, but the device complexity increases due to additional current sink units and control circuits

Engineering Contradiction:
Improvevoltage stabilityVSAvoidtest circuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The test circuit is designed to perform multiple functions: it generates leakage current during standby state to stabilize voltage, and can be controlled to activate only when needed. The current sink unit and control circuits serve both the voltage stabilization purpose and the testing function, reducing the need for separate dedicated components and thereby limiting the increase in device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS7916565B2Semiconductor memory device having test circuit
Publication Date: 2011.03.29 SK HYNIX INC
  • US7916565B2 patent drawing
  • US7916565B2 patent drawing
  • US7916565B2 patent drawing

AI summary

A semiconductor memory device including a test circuit capable of reducing test time includes a test circuit for generating leakage current in the semiconductor memory device in a standby state in response to a test mode signal and a standby signal that provides standby state information of the semiconductor memory device.