Memory Test System With Adaptive Decoder Conversion
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Solution Overview
Problem
As memory capacity increases, the time required to test memory devices for failed cells also increases, leading to higher costs and potential misidentification of good memory cells as bad, resulting in exhausted repair resources during post-package recovery.
Innovation Solution
A memory test system that updates the conversion relation of decoders based on test results, allowing for parallel testing of multiple memory devices, thereby reducing the time required for additional tests and preventing unnecessary resource exhaustion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large number of memory devices are tested sequentially, then comprehensive testing can be performed, but the test time increases significantly
Solution Approach 1:
The patent divides the testing process into two distinct stages: a first test stage that identifies failed memory cells, and a second test stage that performs additional testing only on memory banks containing failed unit blocks. This segmentation allows comprehensive testing while reducing overall test time by avoiding redundant testing of healthy memory banks across multiple devices.
Solution Approach 2:
The patent performs a preliminary first test on all memory devices to identify and classify failed memory cells before proceeding to the second test stage. This preliminary action enables the system to prepare test configurations in advance and focus subsequent testing only on affected areas, thereby reducing total testing time while maintaining comprehensive coverage.
2Reliability
If repair resources are allocated to replace failed memory cells, then memory reliability can be maintained, but repair resources may be exhausted during post-package recovery
Solution Approach 1:
The patent applies local quality by differentiating the treatment of memory banks based on their test results. Memory banks containing failed unit blocks receive additional testing and repair attention, while memory banks without failures are excluded from further processing. This localized approach ensures repair resources are concentrated where needed, preventing resource exhaustion while maintaining reliability.
Solution Approach 2:
The patent implements feedback mechanisms where the results of the first test are used to determine the conversion relations for the second test. The system continuously monitors test outcomes and adjusts resource allocation accordingly, ensuring that repair resources are allocated based on actual failure conditions rather than being exhausted through unnecessary replacements.
3Ease of operation
If the same conversion relation is used for all memory devices, then the testing process is simple, but additional tests cannot be performed in parallel
Solution Approach 1:
The patent transitions from a static, fixed conversion relation to a dynamic, adaptive conversion relation that changes based on test results. The decoder updates conversion relations according to the first test outcomes, enabling the system to perform additional tests in parallel on different memory devices with optimized test configurations, thereby increasing productivity while maintaining operational simplicity.
Solution Approach 2:
The patent changes the parameter of conversion relations dynamically based on test results. By updating the conversion relations according to the first test outcomes, the system enables parallel execution of additional tests on multiple memory devices, increasing testing throughput without complicating the overall testing process.
Data Source
AI summary
A memory test system may include a tester and N memory devices, where N is a positive integer greater than 1. The tester may generate test signals. A K-th memory device of the N memory devices includes a plurality of K-th memory banks and a K-th decoder, where K is each positive integer equal to or smaller than N. The K-th memory banks may be configured to operate based on first internal signals and each of the K-th memory banks includes a plurality of unit blocks. The K-th decoder may be configured to convert the test signals corresponding to the first test to the first internal signals based on a K-th conversion relation and update the K-th conversion relation based on a result of the first test with respect to the K-th memory device.