Memory Test Apparatus Fail Bit Compression

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Solution Overview

Problem

Memory test apparatuses face challenges in efficiently analyzing fail bits due to the limited capacity of fail memory units, which leads to prolonged data transfer times and impractical mounting area requirements when testing multiple devices simultaneously.

Innovation Solution

The memory test apparatus employs a configuration with a first storage medium for temporary retention and compression of test results, and a second storage medium for permanent storage, allowing for parallel processing and interleaved operations to reduce the need for external storage and enhance analysis speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the capacity of the fail memory is increased to store the entire fail bit map, then the analysis speed is improved, but the mounting area is enlarged

Engineering Contradiction:

Improveanalysis speedVSAvoidmounting area

Core Design Contradiction:

SpeedVSArea of stationary object

Solution Approach 1:

The fail bit map storage is segmented into two parts: a first storage medium (fail memory) with smaller capacity for temporary storage and a second storage medium (external storage) with larger capacity for permanent storage. This segmentation allows the system to achieve fast analysis speed using the high-speed fail memory while avoiding the need to increase the mounting area of the fail memory unit.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The first storage medium acts as an intermediary between the fail bit map generation and the second storage medium. It temporarily holds the fail bit map data, enabling fast access and processing while transferring data to the second storage medium at appropriate intervals, thus resolving the contradiction between speed and area.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Quantity of substance

If data is transferred from the fail memory to external storage, then the storage capacity is sufficient, but the transfer time is prolonged

Engineering Contradiction:

Improvestorage capacityVSAvoidtransfer time

Core Design Contradiction:

Quantity of substanceVSLoss of time

Solution Approach 1:

The system performs preliminary actions by continuously writing fail bit map data to the first storage medium during the test process, so that when analysis is needed, the data is already prepared and readily available. This eliminates the need for time-consuming data transfer operations at the moment of analysis.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The first storage medium continuously receives and stores fail bit map data throughout the testing process, maintaining a ready supply of data for analysis. This continuous operation ensures that data is always available when needed, eliminating idle transfer time and keeping the system productive throughout the entire test cycle.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS10636509B2Memory test apparatus

Publication Date: 2020.04.28 KIOXIA CORP

AI summary

A memory test apparatus according to the present embodiment comprises a first storage medium temporarily retaining a test result of memory cells of a device under test in a plurality of divided portions based on data output from the device under test. A first processor reads the divided test result from the first storage medium to compress the test result. A second storage medium is provided to respectively correspond to a plurality of the devices under test and receives the compressed test result from the first processor and saves the compressed test result.