Functional Testing TRIZ Cases
- System of Systems Test Optimization via Parameter Characterization
A test optimization system characterizes constituent parameters to select executable cases from historical knowledge.
- Content Adaptive Signal Probing in Hardware Emulation
Conditional event-based recording extracts essential signal transitions while reducing storage memory size and debug analysis time for hardware emulation.
- Pseudo Failure Generation via System Management Mode Interrupts
Software generates pseudo failures by setting interrupt bits in system management space, enabling universal verification without dedicated hardware.
- Pre-deployment Validation for AI/ML Two-Sided Models
A validation sequence requests and verifies AI/ML models from repositories before deployment.
- Autonomous Functional Agents for System Verification
Autonomous functional agents simulate crowd interactions to determine the functional state of a system under test.
- On-Chip Debug Capture Unit with FIFO Buffer for High-Speed Data
A capture unit paired with a first-in-first-out buffer stores instrumentation data across voltage domains to maintain high-speed logic frequencies.
- Adaptive Remote Service Protocol for Printing Machines
A protocol adaptation level selects suitable data exchange formats to resolve software update delays in printing machine maintenance.
- Memory Read Error Injection via Profiled Retry Vectors
Profiled error injection simulates faults to verify defense algorithms without complex real-time analysis.
- SoC Debug Controller Using Dual UART Baud Rates
A System on Chip debug controller manages two UART controllers with distinct baud rates to route data through shared multiplexers.
- Distributed Test Engine Control via Centralized Database
Central controller manages distributed test engines using a shared control database to reduce message volume while maintaining system synchronization.
- Parallel Processing Unit Idle Cycle Fault Detection
A parallel processing unit inserts test instructions during idle cycles to generate outputs from multiple instances for comparison.
- Memory Test Apparatus Fail Bit Compression
A memory test apparatus compresses fail bit data using a segmented storage architecture to accelerate analysis throughput.
- Magnetic Disk Source-Tracing Regions for Data Recovery
Internal and external source-tracing regions track data modifications on magnetic disks to enable accurate recovery.