Parallel Processing Unit Idle Cycle Fault Detection

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Solution Overview

Problem

Existing processing units configured for parallel processing in safety-critical systems, such as driver-assistance and autonomous vehicle systems, face challenges in efficiently detecting faults within the predetermined time frames required by standards like ASIL B and ASIL D of ISO 26262.

Innovation Solution

A processing unit with a parallel processing engine that includes a test instruction insertion logic to identify idle cycles and insert test instructions for processing, generating test outputs from multiple processing instances, and a check logic to compare these outputs and raise a fault signal if they do not match.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If test instructions are inserted during idle cycles of the parallel processing engine, then fault detection capability is improved, but processing throughput may be reduced due to insertion overhead

Engineering Contradiction:

Improvefault detection capabilityVSAvoidprocessing throughput

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The system performs fault detection tests during idle cycles of the parallel processing engine, before faults occur and affect processing throughput. The test instruction insertion logic identifies idle cycles and inserts test instructions in advance, allowing the system to detect and respond to faults before they impact normal operations.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system implements periodic fault detection by inserting test instructions during idle cycles of the parallel processing engine. This periodic testing mechanism ensures continuous monitoring of processing instances without requiring constant intervention, balancing fault detection needs with processing throughput requirements.

Inventive Principle:

Principle #19Periodic action

2Reliability

If multiple test instructions are inserted to cover all processing instances, then fault detection coverage is improved, but the complexity of the testing system increases

Engineering Contradiction:

Improvefault detection coverageVSAvoidtesting system complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The testing system is segmented into distinct functional components: test instruction insertion logic that identifies idle cycles and inserts test instructions, multiple processing instances that execute tests in parallel, and check logic that compares outputs. This segmentation allows each component to be optimized independently while working together to achieve comprehensive fault detection coverage.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The parallel processing engine performs self-testing by inserting test instructions during its own idle cycles and using its processing instances to execute these tests. The engine compares outputs from different processing instances and raises fault signals if mismatches occur, eliminating the need for external testing equipment and reducing overall system complexity.

Inventive Principle:

Principle #25Self-service

3Speed

If test outputs from multiple processing instances are compared in parallel, then fault detection speed is improved, but the resource consumption increases

Engineering Contradiction:

Improvefault detection speedVSAvoidresource consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The system merges fault detection operations with the existing parallel processing architecture by using the same processing instances for both normal processing and testing. Test instructions are inserted during idle cycles, and the same processing instances that perform normal work execute the tests, combining fault detection with existing computational resources rather than adding separate dedicated testing hardware.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The parallel processing engine maintains continuous useful action by executing test instructions during idle cycles rather than stopping completely for testing. The processing instances remain active, either performing normal processing tasks or executing test instructions, ensuring that the system is never completely idle and that resource consumption is minimized while maintaining fault detection capability.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS20250165259A1Processing unit configured to perform parallel processing

Publication Date: 2025.05.22 IMAGINATION TECH LTD

AI summary

A processing unit configured to perform parallel processing includes a parallel processing engine, the parallel processing engine including a plurality of processing instances configured to process instructions in parallel. Test instruction insertion logic identifies an idle cycle of the parallel processing engine and inserts a test instruction for processing during the idle cycle by each of the plurality of processing instances so as to generate a respective plurality of test outputs. Check logic compares a test output generated during the idle cycle by a first processing instance of the plurality of processing instances with a test output generated during the idle cycle by a second processing instance of the plurality of processing instances, and raises a fault signal if the compared test outputs do not match.