SoC Debug Controller Using Dual UART Baud Rates

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Solution Overview

Problem

Conventional System on Chips (SOCs) face challenges in debugging embedded systems, particularly when the processor crashes, as they cannot collect information through UART connections, making it difficult for developers to diagnose and fix issues.

Innovation Solution

Incorporating a debug controller within the SOC that utilizes a UART port to enable debugging and flash memory updates, even in the event of a processor crash, by employing two UART controllers with different baud rates and multiplexers to manage data transmission and reception, allowing for keyword recognition and execution of debug commands.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a processor crash occurs, then the processor stops functioning properly, but the ability to collect debugging information through UART connection is lost

Engineering Contradiction:
Improvedebugging capabilityVSAvoidoperating state information
Core Design Contradiction:
ReliabilityVSLoss of information

Solution Approach 1:

The system segments the UART communication function into two independent controllers: a first UART controller for normal operation and a second UART controller for debugging. This segmentation allows the debugging function to operate independently when the processor crashes, preventing information loss.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system changes the baud rate parameter of the second UART controller to be different from the first UART controller. This parameter differentiation allows the system to distinguish between normal UART communication and debugging communication, enabling reliable debugging information collection even when the processor crashes.

Inventive Principle:
Principle #35Parameter changes

2Ease of operation

If a simple UART connection is used for debugging, then text input/output is sufficient, but debugging is impossible when the processor crashes

Engineering Contradiction:
ImproveUART debugging simplicityVSAvoiddebugging availability
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The second UART controller is configured to automatically activate when specific keywords are detected in the received data. This self-service mechanism allows the system to switch to debugging mode automatically without requiring external intervention, maintaining ease of operation while improving reliability.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system performs preliminary configuration by setting different baud rates for the two UART controllers before any crash occurs. This preliminary action ensures that when a crash happens, the debugging UART is already prepared and can immediately take over, maintaining both simplicity and reliability.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If two UART controllers with different baud rates are used, then debugging capability is improved, but device complexity increases

Engineering Contradiction:
Improvedebugging availabilityVSAvoidUART controller configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Both UART controllers share the same physical UART port and can perform both normal communication and debugging functions. The first UART controller handles normal operation while the second handles debugging, but either can potentially serve both purposes. This multi-functionality reduces the need for entirely separate hardware paths, mitigating complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system dynamically switches between the first and second UART controllers based on operational needs. A control signal dynamically reconfigures which controller is active for receiving data, allowing the system to adapt to different states (normal operation vs. debugging) without permanent hardware changes, thus managing complexity.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9558086B2System on chip with debug controller and operating method thereof
Publication Date: 2017.01.31 ASPEED TECH
  • US9558086B2 patent drawing
  • US9558086B2 patent drawing
  • US9558086B2 patent drawing

AI summary

A System on Chip (SOC) is disclosed. The SOC comprises a first UART controller, a second UART controller, a debug controller, a processor, a UART port, a first multiplexer and a second multiplexer. The first UART controller and the second UART controller have different baud rates. The UART port has a R×D pin coupled to a R×D pin of the second UART controller. The debug controller generates a control signal with a first state and checks whether a received data from the UART controller is equal to a keyword after power-up or a hardware reset. When the received data from the second UART controller is equal to the keyword, the debug controller generates the control signal with the second state, and starts parsing and executing at least one debug command from the second UART controller.