Pseudo Failure Generation via System Management Mode Interrupts
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Solution Overview
Problem
Existing methods for verifying the monitoring mechanism of information processing apparatuses, such as those using dedicated devices and pseudo generation circuits, lack universality and require technical knowledge, making it difficult to generate pseudo failures or signs of failure outside a vendor's environment without specific hardware or knowledge.
Innovation Solution
A computer-readable non-transitory recording medium containing a program that allows a management unit to generate pseudo failures or signs by shifting the processor to a system management mode, setting pseudo failure information, and generating interrupts, enabling pseudo failure simulation without dedicated devices or specific OS routines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated devices or pseudo generation circuits are used to generate pseudo failures, then the monitoring mechanism can be verified, but the method lacks universality and requires specific technical knowledge and hardware
Solution Approach 1:
The patent creates a virtual copy of the failure condition by setting specific bits in the system management space to indicate a pseudo failure state. Instead of using physical dedicated devices, the system copies the essential characteristics of a real failure into software-controlled data structures that can be accessed and manipulated through standard management interfaces, enabling universal verification across different hardware platforms.
Solution Approach 2:
The patent changes the state parameters of the system management space by setting specific bits (e.g., failure indication bits) to trigger the pseudo failure condition. This parameter-based approach allows the same verification mechanism to work across different hardware configurations without requiring dedicated physical devices, as the failure state is represented through configurable software parameters rather than fixed hardware circuits.
2Reliability
If dedicated devices are used for pseudo failure generation, then verification can be performed, but the device complexity increases
Solution Approach 1:
The patent replaces the mechanical/physical system of dedicated failure generation circuits with a software-based mechanism that operates within the existing system management architecture. By using bit manipulation and interrupt handlers in the firmware layer, the patent eliminates the need for separate physical hardware components, thereby reducing device complexity while maintaining verification capability.
Solution Approach 2:
The patent makes the system management space and interrupt handler serve multiple functions: they are used for normal system management operations and simultaneously for pseudo failure generation and verification. This multi-functionality eliminates the need for dedicated hardware circuits, as existing software components are leveraged to perform both standard management tasks and failure verification, thereby reducing overall device complexity.
3Reliability
If pseudo failure generation requires specific OS routines or dedicated hardware, then verification accuracy can be maintained, but the ease of operation decreases
Solution Approach 1:
The patent enables the system management firmware to self-generate pseudo failures without requiring external dedicated devices or complex OS routines. The interrupt handler and system management space work together in a self-contained manner to create, detect, and clear pseudo failure conditions, making the verification process simple to operate while maintaining accuracy through the use of standardized system management interfaces.
Data Source
AI summary
The information processing apparatus includes a processor and components connected to the processor. In this processor, a failure occurring in any one of the processor and the components connected to the processor itself is recorded in a system space accessible in a system management mode, and an interrupt handler is notified of the occurrence of the failure by an interrupt. The program causes a management computer managing the information processing apparatus to execute shifting the processor to the system management mode, setting information indicating a pseudo failure in the system space, shifting the processor to a non system management mode from the system management mode after setting, and causing the processor to generate the interrupt corresponding to the pseudo failure.