Memory Device Test Pad Connection Circuit for Covered-Pad Testing
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Solution Overview
Problem
Memory devices face challenges in performing test operations in specific test modes after packaging, as the dedicated test pads are covered and not exposed to the outside, preventing direct connection with external test devices.
Innovation Solution
Incorporating a test mode detector circuit to identify test mode entry signals through exposed pins and a test pad connection circuit to electrically couple these pins to dedicated test pads, allowing test mode execution even when the pads are not exposed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the dedicated test pad is covered with an insulating material through the packaging process, then the reliability and protection of the memory device is improved, but the dedicated test pad is not exposed to the outside and cannot be connected to external test devices
Solution Approach 1:
The patent introduces a test mode detector circuit and a test pad connection circuit as intermediary components. The test mode detector circuit detects test mode entry signals through exposed pins, and the test pad connection circuit dynamically connects these pins to the dedicated test pad when test mode is detected. This intermediary mechanism allows external test devices to communicate with the covered dedicated test pad through the pin interface, resolving the contradiction between protecting the test pad and enabling external connection.
2Ease of operation
If the dedicated test pad is exposed to the outside, then external test devices can be directly connected to perform test operations, but the test pad requires additional protection and may increase device complexity
Solution Approach 1:
The patent makes the pins serve multiple functions: they act as normal data or control pins during standard operations, and simultaneously serve as test signal interfaces when test mode is detected. The test pad connection circuit enables this multi-functionality by dynamically routing pin signals to the dedicated test pad only when needed. This eliminates the need for separate exposed test pads, reducing structural complexity while maintaining test accessibility.
3Adaptability or versatility
If a test mode detector circuit and test pad connection circuit are added, then test mode execution is enabled with covered test pads, but the device complexity increases
Solution Approach 1:
The patent implements dynamic circuit configuration where the test pad connection circuit changes its connectivity state based on the detected test mode. During normal operations, the circuit maintains standard pin assignments. When test mode entry signals are detected, the circuit dynamically reconfigures to connect specified pins to the dedicated test pad. This dynamic approach allows the same hardware to adapt to different operational modes without requiring separate fixed test interfaces, optimizing the balance between versatility and complexity.
Data Source
AI summary
A memory device includes a test mode detector circuit that determines whether the memory device has entered a test mode based on at least one test mode entry signal received through at least one pin of a plurality of pins and generates a test mode detection signal, and a test pad connection circuit that electrically couples a first pin of the plurality of pins to a dedicated test pad of the test mode such that a signal applied to the first pin is transmitted to the dedicated test pad based on the test mode detection signal.