Memory Test Pattern Remapping for Data Line Swizzling
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Solution Overview
Problem
The difficulty in accurately writing test patterns into chip interfaces due to data line issues between physical and chip interfaces in memory testing, making it challenging to conduct effective memory tests.
Innovation Solution
A memory test method that involves obtaining a target test pattern, determining corresponding connection information between physical and chip interfaces, remapping this information to generate mapped connection information, and using it to determine an initial test pattern to be written into the physical interfaces, thereby ensuring the target test pattern can be correctly written into the chip interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data lines are used to connect physical interfaces to chip interfaces, then data transmission is enabled, but data line swizzling occurs due to line length differences causing inaccurate test pattern writing
Solution Approach 1:
The patent performs remapping of connection information between physical interfaces and chip interfaces before writing test patterns. This preliminary action establishes the correct correspondence relationship in advance, compensating for data line swizzling issues and ensuring accurate test pattern transmission without requiring physical reconfiguration of data lines.
2Ease of operation
If direct one-to-one connection is used between physical interfaces and chip interfaces, then connection simplicity is maintained, but data line swizzling prevents accurate test pattern writing
Solution Approach 1:
The patent creates a remapped connection information structure that copies and reorganizes the correspondence relationships between physical interfaces and chip interfaces. This virtual mapping model allows the system to handle data line swizzling through software-based remapping while maintaining the physical one-to-one connection structure, thus preserving ease of operation while achieving precise test pattern writing.
3Manufacturing precision
If remapping of connection information is performed, then accurate test pattern writing is achieved, but processing complexity increases
Solution Approach 1:
The patent changes the parameter representation of interface connections by remapping connection information from physical interface indices to chip interface indices based on predetermined correspondence relationships. This parameter transformation approach systematically handles the complexity of data line swizzling through algorithmic remapping rather than physical reconfiguration, achieving precise test pattern writing with controlled processing complexity.
Data Source
AI summary
The present disclosure provides a memory test method, a storage medium and a computer device. The memory test method comprises: obtaining a target test pattern that needs to be written into a plurality of chip interfaces, the plurality of chip interfaces being connected to a plurality of physical interfaces in a one-to-one correspondence; determining second information of the chip interfaces corresponding to first information of the physical interfaces, and using the first information and the second information as corresponding connection information; remapping the corresponding connection information to obtain mapped connection information; and determining, according to the target test pattern and the mapped connection information, an initial test pattern that needs to be written into the physical interfaces.