Memory Test Read Compression for Faster Write Verification
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Solution Overview
Problem
Conventional memory device testing methods, such as write verify tests, are time-consuming and expensive as they require reading each word of a memory array to verify data accuracy, especially as memory sizes increase.
Innovation Solution
Implementing a data compression test mode within memory devices that allows reading one word to indicate the data values of multiple words, utilizing multiple levels of data compression to reduce testing time by comparing bit locations internally and selectively disabling output drivers based on match signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional write verify test methods are used to read each word of the memory array, then data accuracy verification is achieved, but testing time increases significantly
Solution Approach 1:
The patent segments the memory array into multiple banks and divides the verification process into stages. Instead of verifying every word sequentially, the system verifies selected words from each bank in parallel, then uses compression logic to determine if full verification is needed. This segmentation reduces the number of read operations required while maintaining verification completeness.
Solution Approach 2:
The patent implements partial verification by reading only a subset of words from the memory array rather than all words. The compression logic determines whether partial verification is sufficient or if full verification is needed. This partial action approach significantly reduces testing time while maintaining adequate verification through intelligent sampling and compression analysis.
2Quantity of substance
If memory size increases to meet growing storage demands, then storage capacity improves, but testing time and cost increase
Solution Approach 1:
The patent divides large memory arrays into multiple banks that can be tested independently and in parallel. Each bank is further segmented into manageable units for verification. This segmentation allows the testing system to handle large capacities without linearly increasing testing time, as multiple banks can be verified simultaneously through the compression architecture.
Solution Approach 2:
The patent introduces a new dimension of verification through data compression analysis. Instead of verifying data in the traditional time sequence dimension, the system uses compression ratios and patterns as an additional verification dimension. This allows rapid assessment of large memory capacities by analyzing compressed data characteristics rather than examining every bit individually.
3Measurement precision
If full word-by-word reading is performed for verification, then complete data accuracy is ensured, but device complexity and cost increase
Solution Approach 1:
The patent introduces compression logic and control logic as intermediary components between the memory array and the verification system. These intermediaries process raw memory data through compression algorithms, generating condensed representations that are easier to verify. This intermediary layer simplifies the overall testing apparatus by replacing complex bit-by-bit comparison circuits with compression-based verification mechanisms.
Solution Approach 2:
The patent creates compressed copies of memory data for verification purposes rather than working with the full original data sets. These compressed representations retain essential verification information while occupying less space and requiring fewer resources to process. The system verifies the compressed copies and uses this information to determine overall data accuracy, reducing apparatus complexity.
Data Source
AI summary
Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data compression test mode having more than one level of compression. The time necessary to read and verify a repeating test pattern can be reduced as only a fraction of the words of the memory device need be read to determine the ability of the memory device to accurately write and store data values. Output is selectively disabled if a bit location for one word of a group of words has a data value differing from any remaining word of its group of words for a number of groups of words.