Memory Test Scrambler for Parallel Array Configuration
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Solution Overview
Problem
Existing memory testing methods struggle to efficiently test memory arrays with different physical structures using the same test patterns, as they require adaptation to specific memory configurations, leading to inefficiencies and increased testing time.
Innovation Solution
An integrated circuit with a built-in self-test controller and scramblers that translate logical test addresses and data into physical driving addresses and data based on memory configurations, allowing for parallel testing of multiple memory arrays with different configurations using the same test patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If test patterns are adapted to specific memory configurations, then testing accuracy is improved, but device complexity and testing time increase
Solution Approach 1:
The scrambler is designed to work with multiple memory configurations (different MUX levels, memory array dimensions) using the same hardware structure. By translating logical addresses to physical addresses through configurable translation logic, a single universal test pattern can effectively test various memory types without requiring separate test patterns for each configuration.
Solution Approach 2:
The system changes the address translation parameters (MUX level, memory width, memory depth) to adapt to different memory configurations. The scrambler's address translation logic can be reconfigured through parameters to match different memory physical structures, allowing the same test pattern to be applied across varying memory types.
2Measurement precision
If separate test patterns are used for different memory configurations, then testing accuracy is improved, but productivity decreases
Solution Approach 1:
A single test pattern generator produces logical addresses that work universally across different memory configurations. The scrambler handles the configuration-specific address translation, making the test pattern generation universal while maintaining configuration-specific accuracy.
Solution Approach 2:
The scrambler performs preliminary address translation before the test pattern is applied to the memory. By pre-translating logical addresses to physical addresses based on the target memory configuration, the system prepares the test data in advance, eliminating the need for separate test pattern generation for each memory type.
3Measurement precision
If memory arrays with different configurations are tested sequentially, then testing accuracy is maintained, but loss of time increases
Solution Approach 1:
The system segments the address translation function into separate scramblers for different memory configurations. Each scrambler is dedicated to a specific memory block with its own configuration, allowing independent and parallel operation without interfering with other memory tests.
Solution Approach 2:
Multiple memory arrays with different configurations are tested in parallel by merging the test operations. The BIST controller coordinates multiple scramblers and memory blocks simultaneously, combining what would traditionally be sequential tests into parallel operations that reduce total testing time.
Data Source
AI summary
Aspects of the disclosure provide an integrated circuit. The integrated circuit includes a scrambler configured to provide a driving address and associated data to an envelope based on a memory configuration for using a memory array. The driving address and the associated data are used to test the memory array according to a test pattern. The envelope is configured to translate the driving address into a corresponding physical address of the memory array based on the memory configuration.