Nonvolatile Memory Device Thermal Diffusion Write Circuit
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Solution Overview
Problem
Conventional resistance change memories face limitations in increasing the number of memory cells due to high write currents caused by IR drops in word and bit lines, which hinder efficient heating of selected memory elements.
Innovation Solution
The implementation of a nonvolatile memory device that reduces write currents by utilizing thermal energy diffusion between adjacent resistance change memory elements, allowing for simultaneous writing operations that share thermal energy, thereby reducing power consumption and increasing integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional resistance change memory is used, then large write currents are required, but this causes large IR drops in word lines and bit lines, limiting the number of memory cells that can be connected
Solution Approach 1:
The patent merges the heating functions of two adjacent memory elements by simultaneously selecting them with the same polarity voltages. This causes their thermal energy to diffuse into each other, effectively combining their heating effects. As a result, the write current required for each individual element can be reduced while still achieving the necessary temperature increase for resistance change, thereby reducing IR drops and enabling more memory cells to be connected to each word line and bit line.
2Temperature
If a selected memory element is heated, then thermal energy is dissipated into the surroundings, but this prevents efficient heating and increases power consumption
Solution Approach 1:
The patent converts the harmful thermal dissipation into a beneficial effect by deliberately selecting two adjacent memory elements simultaneously with the same polarity. The thermal energy that would normally dissipate into the surroundings is instead captured and shared between the two selected elements through thermal diffusion. This mutual thermal sharing reduces the total power consumption while maintaining effective heating for resistance change.
3Use of energy by moving object
If write current is reduced, then power consumption decreases, but this makes it difficult to efficiently heat the selected memory element for resistance change
Solution Approach 1:
By simultaneously selecting two adjacent memory elements with the same polarity voltages, the patent merges their thermal energy through diffusion. This combined thermal effect compensates for the reduced write current, ensuring that each element still receives sufficient heating for resistance change while reducing overall power consumption.
4Quantity of substance
If the number of memory cells in the array is increased, then storage capacity improves, but this requires more word lines and bit lines, increasing device complexity
Solution Approach 1:
The patent enables a single word line and bit line combination to effectively address and write to two memory cells simultaneously by exploiting thermal diffusion between adjacent elements. This merging approach doubles the storage capacity per wire pair, reducing the total number of word lines and bit lines needed for a given array size, thereby reducing device complexity while increasing storage capacity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces power consumption per bit, increases the number of memory elements in the array, and minimizes thermal disturbances, leading to higher integration and lower production costs while maintaining efficient heating of memory elements.
Implementation Method 1
a selected memory element cannot be efficiently heated because heat is dissipated from the selected memory element into its surroundings
Implementation Method 2
utilizing thermal energy diffusion between adjacent resistance change memory elements
Data Source
AI summary
According to one embodiment, a nonvolatile memory device includes word lines, bit lines, resistance change memory elements, each selectively exhibiting a low or high-resistance state, and a write voltage generating circuit generating a write voltage supplied to the resistance change memory element selected via the bit line selected. The write voltage generating circuit supplies the write voltage to the first and second resistance change memory elements connected to one selected word line and two selected bit lines adjacent to each other in a temporally overlapping manner, and generates the write voltage such that a magnitude of the write voltage supplied to the first resistance change memory element becomes smaller when a write voltage for high-resistance state setting is supplied to the second resistance change memory element than when a write voltage for low-resistance state setting is supplied.