Semiconductor Memory Selective Erasure via Threshold Voltage Raising

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Solution Overview

Problem

Flash memory devices erase entire memory blocks instead of selected pages, leading to reduced data management efficiency.

Innovation Solution

Methods for operating semiconductor memory devices that raise the threshold voltages of programmed cells in selected pages above a predetermined level to convert them into a virtually erased state, allowing for the output of data as erased values during reading operations, and storing information in flag cells to differentiate between first and second erased states.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If erasing is performed on a memory block-by-memory block basis, then all memory cells sharing the P-well can be erased uniformly, but the entire memory block including unselected pages is erased reducing data management efficiency

Engineering Contradiction:
Improveerasing completenessVSAvoiddata management efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The memory block is segmented into selected pages and unselected pages. The invention applies different operations to different segments: selected pages undergo threshold voltage raising to convert programmed cells to erased state, while unselected pages maintain their original state. This selective segmentation resolves the contradiction by enabling precise control over which portions of the memory block are erased.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different quality states are applied to different regions of the memory block. Selected pages receive the threshold voltage raising treatment to achieve erased state, while unselected pages retain their programmed or erased state. This local differentiation allows the system to maintain data management efficiency while ensuring complete erasure where needed.

Inventive Principle:
Principle #3Local quality

2Productivity

If threshold voltages of programmed cells are raised above a predetermined voltage level, then selected memory cells can be converted into a virtually erased state, but additional operational complexity is introduced

Engineering Contradiction:
Improveselective erasure capabilityVSAvoidoperational complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The invention introduces an intermediary state called 'virtually erased state' by raising threshold voltages of selected programmed cells above a predetermined voltage level. This intermediary approach allows selected cells to function as erased cells without requiring a full physical erasure process, thereby enabling selective erasure capability while managing operational complexity through a controlled voltage adjustment mechanism.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The invention changes the threshold voltage parameter of selected programmed cells from below the read voltage level to above the predetermined voltage level. This parameter transformation converts the electrical state of selected cells to match that of erased cells, enabling selective erasure through controlled parameter modification rather than complete physical re-erasure.

Inventive Principle:
Principle #35Parameter changes

3Loss of information

If flag cells are used to store information about the second erased state, then data from first and second erased states can be output with the same value, but memory structure complexity increases

Engineering Contradiction:
Improvedata value consistencyVSAvoidmemory structure complexity
Core Design Contradiction:
Loss of informationVSDevice complexity

Solution Approach 1:

Flag cells serve as intermediary storage elements that record whether selected pages have been converted to the second erased state. These flag cells enable the system to distinguish between first erased state (physical erasure) and second erased state (threshold voltage raising) internally, while presenting a unified erased data value to external readers. This intermediary mechanism ensures data value consistency without requiring external users to understand the internal state differences.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The invention creates a logical copy of the erased state information in flag cells. Instead of requiring the main memory cells to encode both their data state and erasure history, the flag cells store a copy of the erasure status information. This separation allows the main memory cells to present unified erased data values while the flag cells maintain the historical information needed for state differentiation.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS8514633B2Method for operating semiconductor memory device
Publication Date: 2013.08.20 SK HYNIX INC
  • US8514633B2 patent drawing
  • US8514633B2 patent drawing
  • US8514633B2 patent drawing

AI summary

A method for operating a semiconductor memory device includes the steps of: erasing memory cells of a memory block to set the memory cells in a first erased state, programming a part of the memory cells of the memory block to convert them into a programmed state, raising threshold voltages of selected memory cells of the memory block and converting the selected memory cells from the programmed state to a second erased state, and reading data from the memory cells in the first erased state, the programmed state, and the second erased state, and outputting the data read from the memory cells in the first and second erased states with the same value.