3D Memory Through-Contact Layout Using Sacrificial Insulating Layers

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Solution Overview

Problem

In semiconductor memory devices, the formation of memory holes with a high aspect ratio is challenging due to the lamination of conducting layers and interlayer insulating layers, which can lead to increased inner diameters of contact holes and longer distances between through contacts, affecting the efficiency and area of the through contact region.

Innovation Solution

The use of a sacrificial layer as an insulating layer between contacts eliminates the need for additional insulating layers within contact holes, reducing the distance between through contacts and decreasing the area of the through contact region, and the deployment of stopper insulating layers to control chemical etching progress accurately sets the position and area of the through contact region.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conducting layers and interlayer insulating layers are laminated to form memory holes, then the memory structure is achieved, but the inner diameter of contact holes increases and the distance between through contacts increases

Engineering Contradiction:
Improvecontact hole inner diameterVSAvoiddistance between through contacts
Core Design Contradiction:
Manufacturing precisionVSLength of stationary object

Solution Approach 1:

The patent extracts and removes the insulating layer from within the contact hole after the memory hole formation process. This extraction eliminates the need for additional insulating layers in the contact hole region, thereby reducing the inner diameter of contact holes and minimizing the distance between through contacts, which directly resolves the technical contradiction.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent applies a sacrificial insulating layer during the memory hole formation process, which is then removed in a subsequent step. This preliminary action allows the memory structure to be formed correctly while enabling the later removal of the insulating layer to reduce contact hole dimensions and optimize through contact spacing.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If additional insulating layers are placed within contact holes, then insulation is provided, but the area of the through contact region increases

Engineering Contradiction:
Improveinsulation qualityVSAvoidthrough contact region area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent removes the insulating layer from the contact hole region after memory hole formation, extracting only the necessary portion. This selective extraction maintains insulation where needed for memory functionality while eliminating insulating material in the contact hole area, thereby reducing the through contact region area without compromising insulation quality in critical areas.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent applies different treatments to different regions: the insulating layer is retained in the memory hole region to provide necessary insulation, but removed in the contact hole region to minimize area. This local differentiation of insulating layer presence optimizes both insulation quality and contact region area.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration reduces the area of the through contact region, enhances processing convenience, and facilitates faster voltage transfer to conducting layers by minimizing wiring resistance and eliminating the need for additional insulating layers within contact holes.

Implementation Method 1

the deployment of stopper insulating layers to control chemical etching progress accurately sets the position and area of the through contact region

Methodology Applied
Scientific EffectChemical etching:

Data Source

PatentUS11925024B2Semiconductor memory device
Publication Date: 2024.03.05 KIOXIA CORP
  • US11925024B2 patent drawing
  • US11925024B2 patent drawing
  • US11925024B2 patent drawing

AI summary

According to one embodiment, a semiconductor memory device includes a substrate having a first region and a second region arranged in a first direction. The first region includes word line layers and interlayer insulating layers laminated in a second direction, a first semiconductor layer opposed to the word line layers, and an electric charge accumulating film disposed between them. The second region includes a part of the word line layers and the interlayer insulating layers, first insulating layers and a part of the interlayer insulating layers that separate from the word line layers, a contact that has an outer peripheral surface connected to the first insulating layers, and a second insulating layer disposed between the word line layers and the first insulating layers. The first insulating layers have side surfaces connected to the word line layers and side surfaces connected to the second insulating layer.