Memory Timing Path Switching for Setup and Hold Balance
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Solution Overview
Problem
Existing sequential circuits face challenges in balancing setup and hold time requirements across varying operating conditions, leading to metastability, data corruption, and increased power consumption, particularly due to changes in power supply voltage and clock frequency.
Innovation Solution
Implementing signal arrival adjusters with multiple timing paths and a setup/hold selector control signal to dynamically adjust the arrival times of data and clock signals, ensuring both setup and hold time requirements are met across different operating conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the setup time or hold time is violated to increase clock frequency, then performance is improved, but the output value becomes metastable or unpredictable leading to data corruption
Solution Approach 1:
The patent applies dynamics by making the setup and hold times adjustable rather than fixed. The sequential circuit dynamically adapts its timing parameters based on operating conditions (voltage, temperature, frequency) to maintain reliable operation across different performance levels, allowing the circuit to optimize between speed and reliability in real-time
Solution Approach 2:
The patent changes the timing parameters (setup time and hold time) of the sequential circuit based on operating conditions. By adjusting these parameters dynamically, the circuit can operate reliably at higher clock frequencies when conditions permit, while maintaining data integrity across varying voltage and temperature conditions
2Reliability
If the setup time or hold time is increased to ensure stability, then data integrity is maintained, but power consumption increases and latency increases for subsequent combinatorial logic
Solution Approach 1:
The circuit dynamically adjusts its timing parameters based on actual operating conditions rather than using conservative fixed values. This allows the circuit to minimize power consumption and latency by using the smallest necessary setup and hold times that still ensure reliable operation at each moment
Solution Approach 2:
The patent changes the timing parameters adaptively based on operating conditions. When conditions allow for faster operation, the circuit reduces setup and hold times to lower power consumption and latency, while maintaining reliability through continuous adaptation to voltage, temperature, and frequency changes
3Adaptability or versatility
If different power supply voltages and operating clock frequencies are used to balance tradeoffs, then power-performance states are optimized, but balancing setup and hold time requirements across different operating conditions becomes challenging
Solution Approach 1:
The patent implements a universal timing adjustment mechanism that handles multiple operating conditions (different voltages, temperatures, frequencies) through a single adaptive system. This multi-functional approach allows the sequential circuit to maintain reliable operation across all power-performance states without requiring separate timing circuits for each condition
Solution Approach 2:
The circuit uses feedback from operating conditions (voltage, temperature, frequency measurements) to dynamically adjust setup and hold times. This feedback mechanism automatically balances timing requirements across different operating conditions, reducing the complexity of manual timing optimization for each power-performance state
Data Source
AI summary
A system and method for efficiently capturing data by sequential circuits across multiple operating conditions are described. In various implementations, an integrated circuit includes multiple signal arrival adjusters both at its I/O boundaries and across its die. The signal arrival adjuster includes two internal timing paths, each with a respective latency. The signal arrival adjuster receives an input signal, and generates an output signal from the a selected one of the first timing path and the second timing path. The signal arrival adjuster sends the output signal to a sequential circuit. The sequential circuit uses the output signal as one of an input data signal and an input clock signal. The selection between the two timing paths within the signal arrival adjuster aids satisfying the setup and hold time requirements of the sequential circuit.