Semiconductor Package Training for Memory Output Timing Alignment
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Solution Overview
Problem
Semiconductor memory devices experience variations in clock signal timing due to process, voltage, and temperature (PVT) fluctuations, leading to inconsistencies in operating speeds, which can result in data input and output errors during normal operations.
Innovation Solution
A semiconductor package that includes a training operation to adjust the timing of clock signals by programming test codes in multiple electrical fuses, ensuring that the output times of master data and internal data from multiple memory devices become identical, thereby synchronizing their operating speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple memory devices operate simultaneously without timing adjustment, then productivity is improved through parallel operation, but manufacturing precision deteriorates due to PVT variations causing different output time points
Solution Approach 1:
The patent performs timing adjustment through training operations before normal parallel operation. During the training phase, test codes are programmed into fuse circuits to pre-adjust delay times, ensuring that when multiple memory devices operate in parallel, their output time points become identical despite PVT variations.
Solution Approach 2:
The patent changes the delay time parameter of clock signals by programming different test codes into fuse circuits of different memory devices. This adjusts the clock signal timing parameters to compensate for PVT variations, making output time points consistent across devices operating in parallel.
2Manufacturing precision
If clock signal timing is adjusted to synchronize output time points, then manufacturing precision is improved, but device complexity increases due to training operations and fuse programming
Solution Approach 1:
The patent implements self-adjustment where each memory device automatically receives adjusted clock signals based on its own characteristics. The training operation programmatically determines the appropriate delay time for each device and programs it into the fuse circuit, allowing the system to self-calibrate without external intervention during normal operation.
Solution Approach 2:
The patent introduces a controller as an intermediary that manages the training operation and coordinates the programming of test codes into fuse circuits. The controller acts as a mediator between the memory devices and the timing adjustment mechanism, simplifying the overall system architecture by centralizing the adjustment logic.
3Manufacturing precision
If delay adjustment is performed for each memory device, then manufacturing precision is improved through synchronized timing, but ease of manufacture deteriorates due to individual programming requirements
Solution Approach 1:
The timing adjustment is performed during an initial training operation phase before the memory devices are deployed for normal operation. This preliminary programming of fuse circuits with appropriate test codes ensures that subsequent parallel operations maintain precise timing alignment without requiring repeated adjustments.
Solution Approach 2:
The patent changes the delay time parameter of clock signals by programming different test codes into fuse circuits of different memory devices. This adjusts the clock signal timing parameters to compensate for PVT variations, making output time points consistent across devices operating in parallel.
Data Source
AI summary
A semiconductor package includes a first memory device configured to output master data after the start of a training operation, and a second memory device configured to sample internal data based on the master data after the start of the training operation, configured to store test codes that adjust a time point at which the internal data are output when a time point at which the master data are output and the time point at which the internal data are output become identical with each other, and configured to program the stored test codes when the training operation is terminated.