Memory Data Transfer Error Checking for Reliable Programming
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory systems experience performance deterioration and reduced efficiency due to data transfer errors, leading to unreliable data storage and retrieval operations.
Innovation Solution
A memory system with a controller and memory device that performs concurrent or sequential error check operations to verify data integrity, retransferring data as necessary, and utilizing error correction codes like parity bits, CRC bits, and hash code bits to ensure data accuracy during program and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error check operations are performed concurrently or sequentially during data transfer, then data integrity and reliability are improved, but system complexity and processing time increase
Solution Approach 1:
The patent applies preliminary action by performing error check operations (parity check, CRC check, hash code check) concurrently with data transfer operations. The memory device checks for errors during the data transfer process itself, rather than waiting for the transfer to complete, thereby proactively identifying and handling errors before they affect overall system reliability.
Solution Approach 2:
The patent implements continuity of useful action by allowing the error check operation to proceed concurrently with the data transfer operation. Multiple check operations (parity, CRC, hash) are performed continuously during the transfer process, ensuring that error detection is an ongoing activity rather than a separate post-processing step, thus maintaining system productivity while improving reliability.
2Measurement precision
If multiple error check operations (parity, CRC, hash) are performed, then data accuracy is improved, but processing time and operational complexity increase
Solution Approach 1:
The patent merges multiple error check operations (parity check, CRC check, hash code check) into a single integrated error checking process that occurs concurrently with data transfer. Instead of performing these checks sequentially after transfer, they are combined and executed simultaneously during the transfer operation, reducing total processing time while maintaining high data accuracy through multiple verification layers.
Solution Approach 2:
The patent performs error check operations preliminarily during the data transfer process itself. The memory device executes parity, CRC, and hash checks on incoming data while it is being transferred, rather than waiting for complete transfer before verification. This preliminary checking approach ensures data accuracy without adding significant processing time overhead.
3Reliability
If error check operations are completed before program operation, then data reliability is improved, but operational efficiency decreases
Solution Approach 1:
The patent maintains continuity of useful action by overlapping the error check operation with the program operation in time. The error checking process continues concurrently with the data transfer and program execution, rather than completing entirely before program operation begins. This concurrent execution ensures data reliability through thorough checking while preserving operational efficiency by avoiding sequential delays.
Data Source
AI summary
A memory system includes a controller configured to transfer first data for a program operation, and a memory device configured to perform an error check operation for determining whether second data received from the controller are equal to the first data and the program operation for storing the first data.