Memory Transistor Trench Isolation with FLD Implant for Breakdown Control
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Solution Overview
Problem
The limited chip area restricts the expansion of trench isolation width and depth, leading to increased breakdown voltage requirements in high voltage transistors, particularly in 3D NAND memory devices, where electrical breakdown occurs due to the space between the n-well and trench isolation, limiting further improvements in breakdown voltage.
Innovation Solution
A method is introduced to thin the trench isolation above and form a mask layer to ion implant an FLD region below, reducing the width of the FLD region and increasing the breakdown voltage of high voltage transistors, while also simplifying the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If trench isolation width and depth are increased to prevent electrical breakdown, then breakdown voltage resistance is improved, but chip area is consumed and manufacturing complexity increases
Solution Approach 1:
The patent applies local quality by creating a Field Light Doping (FLD) region with specific doping concentration only in the critical area between the n-well and trench isolation, rather than uniformly doping the entire substrate. This localized doping approach enhances breakdown voltage resistance precisely where electrical breakdown occurs, without requiring increased trench isolation dimensions that would consume chip area.
Solution Approach 2:
The patent changes the doping concentration parameter in the substrate by forming an FLD region with a specific doping concentration range (1×10^16 to 1×10^18 atoms/cm³). This parameter change modifies the electrical properties of the substrate in the critical region, enabling improved breakdown voltage resistance through controlled doping rather than through geometric expansion of trench isolation.
2Reliability
If trench isolation width and depth are increased to prevent electrical breakdown, then breakdown voltage resistance is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent applies preliminary action by forming the FLD region through ion implantation before subsequent processing steps. The mask layer is formed with a hole positioned over the trench isolation, and ion implantation is performed through this hole to create the doped region in advance. This preliminary doping action simplifies the overall fabrication process by establishing the critical electrical property early, avoiding the need for complex post-processing or iterative adjustments.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the breakdown voltage of high voltage transistors by extending the space between the n-well and trench isolation, addressing the electrical breakdown issue and reducing fabrication costs.
Implementation Method 1
ion implanting via the hole to form a first doped region below the first trench isolation
Data Source
AI summary
In certain aspects, a semiconductor device includes a substrate, a first trench isolation in the substrate, a first doped region formed below the first trench isolation, a second doped region formed in the substrate, and a first gate structure formed adjacent to the second doped region. The first doped region is an ion implantation region, and a distance between the first doped region and the second doped region is equal to or more than 0.6 μm.