3D Memory Cell Charge Retention via Trap Level Engineering
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Solution Overview
Problem
Current memory devices with three-dimensionally arranged memory cells face challenges in reducing the size of memory cells to increase memory capacity effectively.
Innovation Solution
The memory device incorporates stacked electrode layers, a semiconductor layer, a charge trapping film with a specific trap level, and insulating films to enhance charge storage and retention, allowing for a smaller charge retention region and improved data retention and erasure capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is reduced to increase memory capacity, then memory density increases, but charge retention capability deteriorates
Solution Approach 1:
The patent applies local quality by creating distinct regions with different properties within the memory cell structure. Specifically, the charge trapping film has different trap levels at different locations (first trap level deeper than conduction band, second trap level closer to conduction band), and the insulating film has different dielectric constants in different regions. This allows optimized charge retention in each region while maintaining overall small cell size.
Solution Approach 2:
The patent uses composite materials by combining multiple films with different properties: a charge trapping film with specific trap levels, an insulating film with controlled dielectric constant, and a semiconductor layer. This composite structure enables simultaneous achievement of small size and reliable charge retention through the synergistic effects of different material properties.
2Area of moving object
If charge retention region size is reduced, then memory cell area decreases, but charge storage efficiency worsens
Solution Approach 1:
The patent applies parameter changes by controlling the trap level depths and dielectric constant values to optimize charge storage. The first trap level is positioned deeper than the conduction band while the second trap level is closer to it, and the insulating film's dielectric constant is specifically controlled. These parameter optimizations enable efficient charge storage in a reduced area.
3Reliability
If insulating film dielectric constant is increased to improve charge confinement, then charge retention improves, but manufacturing complexity increases
Solution Approach 1:
The patent applies parameter changes by selecting specific dielectric constant ranges for the insulating film that balance charge confinement performance with manufacturability. Rather than requiring extremely high dielectric constants that would complicate manufacturing, the patent optimizes within a practical range to achieve sufficient charge retention.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables a reduction in memory cell size, increased memory density, and enhanced charge storage efficiency, leading to higher memory capacities.
Implementation Method 1
a charge trapping film that is provided between the electrode layer and the first insulating film. In a flat band state, the charge trapping film may have a first trap level located at a level deeper than a conduction band of the semiconductor layer
Implementation Method 2
the second insulating film may have a second trap level located at a level closer to the conduction band of the semiconductor layer than the first trap level
Data Source
AI summary
A memory device includes plural electrode layers stacked in a first direction, a semiconductor layer interacting with the plural electrode layers and extending in the first direction, a first insulating film provided between the semiconductor layer and at least one electrode layer and extending along the semiconductor layer in the first direction, and a charge trapping film provided between the electrode layer and the first insulating film. The memory device further includes a second insulating film provided between the charge trapping film and the first insulating film and in contact with the first insulating film. In a flat band state, the charge trapping film has a first trap level located at a level deeper than a conduction band of the semiconductor layer and the second insulating film has a second trap level that is closer to the conduction band of the semiconductor layer than the first trap level.