Semiconductor Memory Device Under Drive Voltage Control
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Solution Overview
Problem
Current semiconductor memory devices face challenges in improving program speed due to voltage level maintenance issues during verify operations, where the voltage level of the selected word line is often higher than the verify voltages, leading to inefficiencies in program loops.
Innovation Solution
The semiconductor memory device employs a control logic to apply a first under drive voltage at a lower voltage level than the verify voltage, followed by sequential verify voltages, and optionally uses second and third under drive voltages to quickly decrease the voltage level, optimizing the program operation by adaptively determining these voltages based on program loops and verify voltage differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the voltage level of the selected word line is maintained at a high level during verify operations, then the program operation can be performed, but the program speed decreases due to inefficiencies in program loops
Solution Approach 1:
The patent applies dynamic voltage adjustment by changing the voltage level of the selected word line from a high program voltage to a lower first under drive voltage between program and verify operations. This dynamic adjustment optimizes the timing and voltage levels during program loops, reducing the time spent maintaining high voltage levels and thereby improving program speed.
Solution Approach 2:
The patent applies preliminary action by setting the voltage level of the selected word line to a first under drive voltage before the verify operation begins. This preliminary voltage adjustment prepares the system for the upcoming verify operation, reducing the time required to transition from program to verify mode and improving overall program speed.
2Productivity
If multiple under drive voltages are applied to quickly decrease the voltage level, then the program speed is enhanced, but the device complexity increases
Solution Approach 1:
The patent segments the voltage adjustment process into multiple distinct voltage levels: a first under drive voltage applied between program and verify operations, and a second under drive voltage applied between verify operations. This segmentation allows for optimized voltage transitions at different stages of the program loop, enhancing program speed while managing complexity through structured voltage control.
Solution Approach 2:
The patent applies different voltage levels (first under drive voltage and second under drive voltage) at different locations in the program loop timeline. The first under drive voltage is applied specifically between program and verify operations, while the second under drive voltage is applied between verify operations. This local quality approach optimizes voltage control for specific operational phases, improving program speed with targeted complexity.
Data Source
AI summary
A semiconductor memory device includes a memory cell array, a peripheral circuit, and a control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit performs a program operation on selected memory cells among the plurality of memory cells. The control logic controls the program operation of the peripheral circuit. The program operation includes a plurality of program loops. The control logic is configured to control the peripheral circuit to apply a program voltage to a select word line that is connected to the selected memory cells, apply a first under drive voltage that is determined based on at least one verify voltage to the select word line, and apply the at least one verify voltage to the select word line in each of the plurality of program loops. The first under drive voltage is at a lower voltage level than the at least one verify voltage.